Search

Alexander G. Ghyka

Examiner (ID: 18931, Phone: (571)272-1669 , Office: P/2812 )

Most Active Art Unit
2812
Art Unit(s)
1754, 1106, 2812, 2899, 1105
Total Applications
3052
Issued Applications
2465
Pending Applications
254
Abandoned Applications
366

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17708540 [patent_doc_number] => 20220208548 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-30 [patent_title] => VERTICAL NANOWIRE SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR [patent_app_type] => utility [patent_app_number] => 17/695336 [patent_app_country] => US [patent_app_date] => 2022-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4397 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 329 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17695336 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/695336
Vertical nanowire semiconductor device and manufacturing method therefor Mar 14, 2022 Issued
Array ( [id] => 18913126 [patent_doc_number] => 11876115 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-01-16 [patent_title] => Alignment-tolerant gallium oxide device [patent_app_type] => utility [patent_app_number] => 17/686546 [patent_app_country] => US [patent_app_date] => 2022-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 2876 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 234 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17686546 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/686546
Alignment-tolerant gallium oxide device Mar 3, 2022 Issued
Array ( [id] => 17738011 [patent_doc_number] => 20220223473 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-14 [patent_title] => TOP VIA ON SUBTRACTIVELY ETCHED CONDUCTIVE LINE [patent_app_type] => utility [patent_app_number] => 17/683579 [patent_app_country] => US [patent_app_date] => 2022-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6067 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17683579 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/683579
Top via on subtractively etched conductive line Feb 28, 2022 Issued
Array ( [id] => 19176087 [patent_doc_number] => 20240162061 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-16 [patent_title] => SUBSTRATE PROCESSING APPARATUS, SUBSTRATE PROCESSING SYSTEM, AND SUBSTRATE PROCESSING METHOD [patent_app_type] => utility [patent_app_number] => 18/549934 [patent_app_country] => US [patent_app_date] => 2022-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6124 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18549934 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/549934
SUBSTRATE PROCESSING APPARATUS, SUBSTRATE PROCESSING SYSTEM, AND SUBSTRATE PROCESSING METHOD Feb 27, 2022 Pending
Array ( [id] => 20532029 [patent_doc_number] => 12550481 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-02-10 [patent_title] => Method to improve performances of tunnel junctions grown by metal organic chemical vapor deposition [patent_app_type] => utility [patent_app_number] => 18/546484 [patent_app_country] => US [patent_app_date] => 2022-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 8641 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18546484 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/546484
Method to improve performances of tunnel junctions grown by metal organic chemical vapor deposition Feb 27, 2022 Issued
Array ( [id] => 18570449 [patent_doc_number] => 20230260786 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-17 [patent_title] => SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 17/674674 [patent_app_country] => US [patent_app_date] => 2022-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7730 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17674674 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/674674
Semiconductor structure and method for forming the same Feb 16, 2022 Issued
Array ( [id] => 18570724 [patent_doc_number] => 20230261061 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-17 [patent_title] => METHOD FOR PREPARING RECESSED GATE STRUCTURE WITH PROTECTION LAYER [patent_app_type] => utility [patent_app_number] => 17/672138 [patent_app_country] => US [patent_app_date] => 2022-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4767 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17672138 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/672138
Method for preparing recessed gate structure with protection layer Feb 14, 2022 Issued
Array ( [id] => 19328785 [patent_doc_number] => 12046474 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-07-23 [patent_title] => Wafer and manufacturing method of wafer [patent_app_type] => utility [patent_app_number] => 17/670510 [patent_app_country] => US [patent_app_date] => 2022-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 19 [patent_no_of_words] => 6653 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17670510 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/670510
Wafer and manufacturing method of wafer Feb 13, 2022 Issued
Array ( [id] => 17615385 [patent_doc_number] => 20220157665 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-19 [patent_title] => SEMICONDUCTOR DEVICE WITH FIN END SPACER PLUG AND METHOD OF MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 17/591906 [patent_app_country] => US [patent_app_date] => 2022-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10354 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17591906 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/591906
Semiconductor device with fin end spacer plug and method of manufacturing the same Feb 2, 2022 Issued
Array ( [id] => 18704639 [patent_doc_number] => 11791156 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-17 [patent_title] => Method for manufacturing semiconductor device having gallium-based compound semiconductor layer [patent_app_type] => utility [patent_app_number] => 17/591202 [patent_app_country] => US [patent_app_date] => 2022-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 2900 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17591202 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/591202
Method for manufacturing semiconductor device having gallium-based compound semiconductor layer Feb 1, 2022 Issued
Array ( [id] => 17764950 [patent_doc_number] => 20220238563 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-28 [patent_title] => Semiconductor Device And Method For Manufacturing The Same [patent_app_type] => utility [patent_app_number] => 17/586947 [patent_app_country] => US [patent_app_date] => 2022-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 29785 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -3 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17586947 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/586947
Semiconductor device and method for manufacturing the same Jan 27, 2022 Issued
Array ( [id] => 17765030 [patent_doc_number] => 20220238643 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-28 [patent_title] => COUPLED GUARD RINGS FOR EDGE TERMINATION [patent_app_type] => utility [patent_app_number] => 17/584215 [patent_app_country] => US [patent_app_date] => 2022-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15256 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17584215 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/584215
Coupled guard rings for edge termination Jan 24, 2022 Issued
Array ( [id] => 17599403 [patent_doc_number] => 20220148977 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-12 [patent_title] => Method and Structure for Semiconductor Interconnect [patent_app_type] => utility [patent_app_number] => 17/582648 [patent_app_country] => US [patent_app_date] => 2022-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6991 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17582648 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/582648
Method and structure for semiconductor interconnect Jan 23, 2022 Issued
Array ( [id] => 19919765 [patent_doc_number] => 12295161 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-05-06 [patent_title] => Trench isolation having three portions with different materials, and LDMOS FET including same [patent_app_type] => utility [patent_app_number] => 17/582550 [patent_app_country] => US [patent_app_date] => 2022-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 0 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17582550 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/582550
Trench isolation having three portions with different materials, and LDMOS FET including same Jan 23, 2022 Issued
Array ( [id] => 19444476 [patent_doc_number] => 12094765 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-09-17 [patent_title] => Integrated circuit package and method [patent_app_type] => utility [patent_app_number] => 17/648140 [patent_app_country] => US [patent_app_date] => 2022-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 37 [patent_figures_cnt] => 41 [patent_no_of_words] => 15579 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17648140 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/648140
Integrated circuit package and method Jan 16, 2022 Issued
Array ( [id] => 18857231 [patent_doc_number] => 11854823 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-12-26 [patent_title] => Integrated circuit device [patent_app_type] => utility [patent_app_number] => 17/574414 [patent_app_country] => US [patent_app_date] => 2022-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 49 [patent_no_of_words] => 9227 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17574414 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/574414
Integrated circuit device Jan 11, 2022 Issued
Array ( [id] => 18473318 [patent_doc_number] => 20230207606 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-29 [patent_title] => LIGHT EMITTING DIODE WITH ANGLE-DEPENDENT OPTICAL FILTER [patent_app_type] => utility [patent_app_number] => 17/564212 [patent_app_country] => US [patent_app_date] => 2021-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 26433 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17564212 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/564212
LIGHT EMITTING DIODE WITH ANGLE-DEPENDENT OPTICAL FILTER Dec 28, 2021 Abandoned
Array ( [id] => 17901101 [patent_doc_number] => 20220310763 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-29 [patent_title] => DISPLAY APPARATUS [patent_app_type] => utility [patent_app_number] => 17/564622 [patent_app_country] => US [patent_app_date] => 2021-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18580 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17564622 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/564622
Display apparatus Dec 28, 2021 Issued
Array ( [id] => 17551849 [patent_doc_number] => 20220123191 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-21 [patent_title] => LED MODULE AND DISPLAY DEVICE HAVING LED MODULE [patent_app_type] => utility [patent_app_number] => 17/563084 [patent_app_country] => US [patent_app_date] => 2021-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6706 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17563084 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/563084
LED MODULE AND DISPLAY DEVICE HAVING LED MODULE Dec 27, 2021 Pending
Array ( [id] => 19567909 [patent_doc_number] => 12142691 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-11-12 [patent_title] => Thin film transistor, method for manufacturing the thin film transistor and display device comprising the thin film transistor [patent_app_type] => utility [patent_app_number] => 17/563887 [patent_app_country] => US [patent_app_date] => 2021-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 32 [patent_no_of_words] => 14877 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 237 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17563887 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/563887
Thin film transistor, method for manufacturing the thin film transistor and display device comprising the thin film transistor Dec 27, 2021 Issued
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