Search

Alexander G. Ghyka

Examiner (ID: 13103, Phone: (571)272-1669 , Office: P/2812 )

Most Active Art Unit
2812
Art Unit(s)
2812, 1106, 1754, 1105, 2899
Total Applications
3009
Issued Applications
2443
Pending Applications
238
Abandoned Applications
365

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 11760217 [patent_doc_number] => 20170207086 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-07-20 [patent_title] => 'PREPARATION METHODS OF LOW TEMPERATURE POLY-SILICON THIN FILM AND TRANSISTOR AND LASER CRYSTALLIZATION APPARATUS' [patent_app_type] => utility [patent_app_number] => 15/228140 [patent_app_country] => US [patent_app_date] => 2016-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3767 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15228140 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/228140
Preparation methods of low temperature poly-silicon thin film and transistor and laser crystallization apparatus Aug 3, 2016 Issued
Array ( [id] => 13173809 [patent_doc_number] => 10103026 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-10-16 [patent_title] => Methods of forming material layer [patent_app_type] => utility [patent_app_number] => 15/227089 [patent_app_country] => US [patent_app_date] => 2016-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 34 [patent_figures_cnt] => 34 [patent_no_of_words] => 12993 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15227089 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/227089
Methods of forming material layer Aug 2, 2016 Issued
Array ( [id] => 11811503 [patent_doc_number] => 09716077 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-07-25 [patent_title] => 'Wire connecting method and terminal' [patent_app_type] => utility [patent_app_number] => 15/227601 [patent_app_country] => US [patent_app_date] => 2016-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 15 [patent_no_of_words] => 4051 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15227601 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/227601
Wire connecting method and terminal Aug 2, 2016 Issued
Array ( [id] => 11446204 [patent_doc_number] => 20170047226 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-02-16 [patent_title] => 'FORMING A CONTACT FOR A TALL FIN TRANSISTOR' [patent_app_type] => utility [patent_app_number] => 15/227142 [patent_app_country] => US [patent_app_date] => 2016-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 4343 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15227142 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/227142
Forming a contact for a tall fin transistor Aug 2, 2016 Issued
Array ( [id] => 11918508 [patent_doc_number] => 09786700 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-10-10 [patent_title] => 'Low temperature poly-silicon (LTPS) thin film transistors (TFT) units and the manufacturing method thereof' [patent_app_type] => utility [patent_app_number] => 15/227696 [patent_app_country] => US [patent_app_date] => 2016-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 1900 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15227696 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/227696
Low temperature poly-silicon (LTPS) thin film transistors (TFT) units and the manufacturing method thereof Aug 2, 2016 Issued
Array ( [id] => 11293868 [patent_doc_number] => 20160343800 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-11-24 [patent_title] => 'METHOD OF FORMING A SEMICONDUCTOR DIE' [patent_app_type] => utility [patent_app_number] => 15/225054 [patent_app_country] => US [patent_app_date] => 2016-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 16316 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 22 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15225054 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/225054
METHOD OF FORMING A SEMICONDUCTOR DIE Jul 31, 2016 Abandoned
Array ( [id] => 12918391 [patent_doc_number] => 20180197973 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-07-12 [patent_title] => MANUFACTURING METHOD OF TOP GATE THIN-FILM TRANSISTOR [patent_app_type] => utility [patent_app_number] => 15/121040 [patent_app_country] => US [patent_app_date] => 2016-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3135 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 271 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15121040 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/121040
Manufacturing method of top gate thin-film transistor Jul 14, 2016 Issued
Array ( [id] => 13098841 [patent_doc_number] => 10068765 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-09-04 [patent_title] => Multi-step system and method for curing a dielectric film [patent_app_type] => utility [patent_app_number] => 15/204279 [patent_app_country] => US [patent_app_date] => 2016-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 6178 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 247 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15204279 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/204279
Multi-step system and method for curing a dielectric film Jul 6, 2016 Issued
Array ( [id] => 13862457 [patent_doc_number] => 10192956 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-01-29 [patent_title] => Method for producing fin structures of a semiconductor device in a substrate [patent_app_type] => utility [patent_app_number] => 15/204853 [patent_app_country] => US [patent_app_date] => 2016-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 42 [patent_no_of_words] => 5461 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15204853 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/204853
Method for producing fin structures of a semiconductor device in a substrate Jul 6, 2016 Issued
Array ( [id] => 13257471 [patent_doc_number] => 10141433 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-11-27 [patent_title] => Method of manufacturing thin film transistor [patent_app_type] => utility [patent_app_number] => 15/118881 [patent_app_country] => US [patent_app_date] => 2016-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 2466 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15118881 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/118881
Method of manufacturing thin film transistor Jun 29, 2016 Issued
Array ( [id] => 11551621 [patent_doc_number] => 09620479 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-04-11 [patent_title] => '3D bonded semiconductor structure with an embedded resistor' [patent_app_type] => utility [patent_app_number] => 15/199129 [patent_app_country] => US [patent_app_date] => 2016-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 6581 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15199129 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/199129
3D bonded semiconductor structure with an embedded resistor Jun 29, 2016 Issued
Array ( [id] => 11367250 [patent_doc_number] => 20170005230 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-01-05 [patent_title] => 'Light-emitting device' [patent_app_type] => utility [patent_app_number] => 15/199152 [patent_app_country] => US [patent_app_date] => 2016-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2940 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15199152 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/199152
Light-emitting device Jun 29, 2016 Issued
Array ( [id] => 12896098 [patent_doc_number] => 20180190541 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-07-05 [patent_title] => FAN-OUT LINE ARRANGEMENT, DISPLAY PANEL AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 15/533693 [patent_app_country] => US [patent_app_date] => 2016-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4379 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15533693 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/533693
FAN-OUT LINE ARRANGEMENT, DISPLAY PANEL AND MANUFACTURING METHOD THEREOF Jun 29, 2016 Abandoned
Array ( [id] => 12122360 [patent_doc_number] => 20180005946 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-01-04 [patent_title] => 'HIGH RESOLUTION SOLDER RESIST MATERIAL FOR SILICON BRIDGE APPLICATION' [patent_app_type] => utility [patent_app_number] => 15/199219 [patent_app_country] => US [patent_app_date] => 2016-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7679 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15199219 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/199219
High resolution solder resist material for silicon bridge application Jun 29, 2016 Issued
Array ( [id] => 12122355 [patent_doc_number] => 20180005941 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-01-04 [patent_title] => 'SEMICONDUCTOR DEVICE INCLUDING A POROUS DIELECTRIC LAYER, AND METHOD OF FORMING THE SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 15/199321 [patent_app_country] => US [patent_app_date] => 2016-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4997 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15199321 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/199321
Semiconductor device including a porous dielectric layer, and method of forming the semiconductor device Jun 29, 2016 Issued
Array ( [id] => 11118101 [patent_doc_number] => 20160315076 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-10-27 [patent_title] => 'ELECTROSTATIC DISCHARGE DEVICES AND METHODS OF MANUFACTURE' [patent_app_type] => utility [patent_app_number] => 15/198197 [patent_app_country] => US [patent_app_date] => 2016-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4463 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15198197 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/198197
Electrostatic discharge devices and methods of manufacture Jun 29, 2016 Issued
Array ( [id] => 11898133 [patent_doc_number] => 09768072 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-09-19 [patent_title] => 'Fabrication of a vertical fin field effect transistor with reduced dimensional variations' [patent_app_type] => utility [patent_app_number] => 15/199352 [patent_app_country] => US [patent_app_date] => 2016-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 20 [patent_no_of_words] => 9704 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15199352 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/199352
Fabrication of a vertical fin field effect transistor with reduced dimensional variations Jun 29, 2016 Issued
Array ( [id] => 11740354 [patent_doc_number] => 09704949 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-07-11 [patent_title] => 'Active area designs for charge-balanced diodes' [patent_app_type] => utility [patent_app_number] => 15/199262 [patent_app_country] => US [patent_app_date] => 2016-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 22 [patent_no_of_words] => 9506 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15199262 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/199262
Active area designs for charge-balanced diodes Jun 29, 2016 Issued
Array ( [id] => 13243387 [patent_doc_number] => 10134905 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-11-20 [patent_title] => Semiconductor device including wrap around contact, and method of forming the semiconductor device [patent_app_type] => utility [patent_app_number] => 15/199334 [patent_app_country] => US [patent_app_date] => 2016-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 54 [patent_no_of_words] => 9290 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15199334 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/199334
Semiconductor device including wrap around contact, and method of forming the semiconductor device Jun 29, 2016 Issued
Array ( [id] => 11446403 [patent_doc_number] => 20170047424 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-02-16 [patent_title] => 'GROWING GROUPS III-V LATERAL NANOWIRE CHANNELS' [patent_app_type] => utility [patent_app_number] => 15/194728 [patent_app_country] => US [patent_app_date] => 2016-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2265 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15194728 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/194728
Growing groups III-V lateral nanowire channels Jun 27, 2016 Issued
Menu