Search

Alexander G. Ghyka

Examiner (ID: 16688, Phone: (571)272-1669 , Office: P/2812 )

Most Active Art Unit
2812
Art Unit(s)
2812, 1754, 1106, 1105, 2899
Total Applications
3004
Issued Applications
2438
Pending Applications
238
Abandoned Applications
365

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19335550 [patent_doc_number] => 20240249980 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-25 [patent_title] => FABRICATION OF A VERTICAL FIN FIELD EFFECT TRANSISTOR WITH REDUCED DIMENSIONAL VARIATIONS [patent_app_type] => utility [patent_app_number] => 18/243501 [patent_app_country] => US [patent_app_date] => 2023-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9351 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18243501 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/243501
Fabrication of a vertical fin field effect transistor with reduced dimensional variations Sep 6, 2023 Issued
Array ( [id] => 19102734 [patent_doc_number] => 20240121962 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-04-11 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 18/461326 [patent_app_country] => US [patent_app_date] => 2023-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17644 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18461326 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/461326
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE Sep 4, 2023 Pending
Array ( [id] => 19252498 [patent_doc_number] => 20240203495 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-20 [patent_title] => SEMICONDUCTOR MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/460325 [patent_app_country] => US [patent_app_date] => 2023-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11362 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 464 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18460325 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/460325
Semiconductor memory device Aug 31, 2023 Issued
Array ( [id] => 19023367 [patent_doc_number] => 20240079538 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-07 [patent_title] => LIGHT-EMITTING DEVICE AND METHOD FOR MANUFACTURING LIGHT-EMITTING DEVICE [patent_app_type] => utility [patent_app_number] => 18/455755 [patent_app_country] => US [patent_app_date] => 2023-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7133 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18455755 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/455755
LIGHT-EMITTING DEVICE AND METHOD FOR MANUFACTURING LIGHT-EMITTING DEVICE Aug 24, 2023 Pending
Array ( [id] => 19328781 [patent_doc_number] => 12046470 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-07-23 [patent_title] => Method for making semiconductor device including a superlattice and enriched silicon 28 epitaxial layer [patent_app_type] => utility [patent_app_number] => 18/237196 [patent_app_country] => US [patent_app_date] => 2023-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 13 [patent_no_of_words] => 6011 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18237196 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/237196
Method for making semiconductor device including a superlattice and enriched silicon 28 epitaxial layer Aug 22, 2023 Issued
Array ( [id] => 19269708 [patent_doc_number] => 20240213413 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-27 [patent_title] => DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 18/235245 [patent_app_country] => US [patent_app_date] => 2023-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10596 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -25 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18235245 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/235245
DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME Aug 16, 2023 Pending
Array ( [id] => 18991053 [patent_doc_number] => 20240063022 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-22 [patent_title] => WAFER BONDING PROCESS WITH REDUCED OVERLAY DISTORTION [patent_app_type] => utility [patent_app_number] => 18/450083 [patent_app_country] => US [patent_app_date] => 2023-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10682 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18450083 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/450083
WAFER BONDING PROCESS WITH REDUCED OVERLAY DISTORTION Aug 14, 2023 Pending
Array ( [id] => 18818741 [patent_doc_number] => 20230393081 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-07 [patent_title] => SYSTEMS AND METHODS FOR WAFER BOND MONITORING [patent_app_type] => utility [patent_app_number] => 18/448766 [patent_app_country] => US [patent_app_date] => 2023-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9809 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18448766 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/448766
Systems and methods for wafer bond monitoring Aug 10, 2023 Issued
Array ( [id] => 20360134 [patent_doc_number] => 12476139 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-18 [patent_title] => Integrated circuit package and method [patent_app_type] => utility [patent_app_number] => 18/446521 [patent_app_country] => US [patent_app_date] => 2023-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 37 [patent_figures_cnt] => 41 [patent_no_of_words] => 10311 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18446521 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/446521
Integrated circuit package and method Aug 8, 2023 Issued
Array ( [id] => 18833803 [patent_doc_number] => 20230402330 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-14 [patent_title] => MID-MANUFACTURING SEMICONDUCTOR WAFER LAYER TESTING [patent_app_type] => utility [patent_app_number] => 18/230664 [patent_app_country] => US [patent_app_date] => 2023-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12179 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18230664 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/230664
Mid-manufacturing semiconductor wafer layer testing Aug 6, 2023 Issued
Array ( [id] => 19758046 [patent_doc_number] => 20250046611 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-06 [patent_title] => NEUTRAL STRESS DIAMOND-LIKE CARBON [patent_app_type] => utility [patent_app_number] => 18/364507 [patent_app_country] => US [patent_app_date] => 2023-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10183 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18364507 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/364507
NEUTRAL STRESS DIAMOND-LIKE CARBON Aug 2, 2023 Pending
Array ( [id] => 20531962 [patent_doc_number] => 12550414 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-02-10 [patent_title] => Wafer-level die singulation using buried sacrificial structure [patent_app_type] => utility [patent_app_number] => 18/362921 [patent_app_country] => US [patent_app_date] => 2023-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 27 [patent_no_of_words] => 3299 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18362921 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/362921
Wafer-level die singulation using buried sacrificial structure Jul 30, 2023 Issued
Array ( [id] => 19733787 [patent_doc_number] => 12211789 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-01-28 [patent_title] => Three dimensional integrated circuit and fabrication thereof [patent_app_type] => utility [patent_app_number] => 18/362731 [patent_app_country] => US [patent_app_date] => 2023-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 52 [patent_figures_cnt] => 52 [patent_no_of_words] => 15128 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18362731 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/362731
Three dimensional integrated circuit and fabrication thereof Jul 30, 2023 Issued
Array ( [id] => 18812580 [patent_doc_number] => 20230386917 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-30 [patent_title] => Bottom-up Formation of Contact Plugs [patent_app_type] => utility [patent_app_number] => 18/362676 [patent_app_country] => US [patent_app_date] => 2023-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8195 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18362676 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/362676
Bottom-up formation of contact plugs Jul 30, 2023 Issued
Array ( [id] => 19858185 [patent_doc_number] => 12261036 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-03-25 [patent_title] => Forming low-stress silicon nitride layer through hydrogen treatment [patent_app_type] => utility [patent_app_number] => 18/358508 [patent_app_country] => US [patent_app_date] => 2023-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 30 [patent_no_of_words] => 8250 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18358508 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/358508
Forming low-stress silicon nitride layer through hydrogen treatment Jul 24, 2023 Issued
Array ( [id] => 18774295 [patent_doc_number] => 20230369126 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-16 [patent_title] => SEMICONDUCTOR DEVICE WITH FIN END SPACER PLUG AND METHOD OF MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 18/226185 [patent_app_country] => US [patent_app_date] => 2023-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10373 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18226185 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/226185
Semiconductor device with fin end spacer plug and method of manufacturing the same Jul 24, 2023 Issued
Array ( [id] => 18757487 [patent_doc_number] => 20230360949 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-09 [patent_title] => SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/356212 [patent_app_country] => US [patent_app_date] => 2023-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5215 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18356212 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/356212
Semiconductor package and manufacturing method thereof Jul 19, 2023 Issued
Array ( [id] => 18906272 [patent_doc_number] => 20240021757 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-18 [patent_title] => DISPLAY DEVICE, METHOD FOR MANUFACTURING DISPLAY DEVICE, AND METHOD FOR INSPECTING DISPLAY DEVICE [patent_app_type] => utility [patent_app_number] => 18/350774 [patent_app_country] => US [patent_app_date] => 2023-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6039 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18350774 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/350774
DISPLAY DEVICE, METHOD FOR MANUFACTURING DISPLAY DEVICE, AND METHOD FOR INSPECTING DISPLAY DEVICE Jul 11, 2023 Pending
Array ( [id] => 20175922 [patent_doc_number] => 12394677 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-08-19 [patent_title] => Semiconductor structure with overlay mark and system for manufacturing the same [patent_app_type] => utility [patent_app_number] => 18/219846 [patent_app_country] => US [patent_app_date] => 2023-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 29 [patent_no_of_words] => 5593 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18219846 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/219846
Semiconductor structure with overlay mark and system for manufacturing the same Jul 9, 2023 Issued
Array ( [id] => 19696466 [patent_doc_number] => 20250015011 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-09 [patent_title] => METHOD OF FORMING MARK ON SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 18/346840 [patent_app_country] => US [patent_app_date] => 2023-07-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5652 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18346840 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/346840
Method of forming mark on semiconductor device Jul 3, 2023 Issued
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