Search

Alexander G. Ghyka

Examiner (ID: 13103, Phone: (571)272-1669 , Office: P/2812 )

Most Active Art Unit
2812
Art Unit(s)
2812, 1106, 1754, 1105, 2899
Total Applications
3009
Issued Applications
2443
Pending Applications
238
Abandoned Applications
365

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 11004975 [patent_doc_number] => 20160201925 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-07-14 [patent_title] => 'CALIBRATION AND MONITORING OF A KITCHEN HOOD SYSTEM' [patent_app_type] => utility [patent_app_number] => 14/619356 [patent_app_country] => US [patent_app_date] => 2015-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 17207 [patent_no_of_claims] => 48 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14619356 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/619356
CALIBRATION AND MONITORING OF A KITCHEN HOOD SYSTEM Feb 10, 2015 Abandoned
Array ( [id] => 11698551 [patent_doc_number] => 09688453 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-06-27 [patent_title] => 'Heat dissipation in hermetically-sealed packaged devices' [patent_app_type] => utility [patent_app_number] => 14/617078 [patent_app_country] => US [patent_app_date] => 2015-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 2756 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14617078 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/617078
Heat dissipation in hermetically-sealed packaged devices Feb 8, 2015 Issued
Array ( [id] => 11807289 [patent_doc_number] => 09548372 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-01-17 [patent_title] => 'Semiconductor device with tunable work function' [patent_app_type] => utility [patent_app_number] => 14/609138 [patent_app_country] => US [patent_app_date] => 2015-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 7523 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 214 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14609138 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/609138
Semiconductor device with tunable work function Jan 28, 2015 Issued
Array ( [id] => 10247954 [patent_doc_number] => 20150132950 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-05-14 [patent_title] => 'SEMICONDUCTOR PACKAGES, METHODS OF MANUFACTURING THE SAME, AND SEMICONDUCTOR PACKAGE STRUCTURES INCLUDING THE SAME' [patent_app_type] => utility [patent_app_number] => 14/601215 [patent_app_country] => US [patent_app_date] => 2015-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 37 [patent_figures_cnt] => 37 [patent_no_of_words] => 23991 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14601215 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/601215
Semiconductor packages, methods of manufacturing the same, and semiconductor package structures including the same Jan 19, 2015 Issued
Array ( [id] => 11453223 [patent_doc_number] => 09576875 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-02-21 [patent_title] => 'Methods for manufacturing a chip arrangement, methods for manufacturing a chip package, a chip package and chip arrangements' [patent_app_type] => utility [patent_app_number] => 14/591014 [patent_app_country] => US [patent_app_date] => 2015-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 17 [patent_no_of_words] => 7568 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14591014 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/591014
Methods for manufacturing a chip arrangement, methods for manufacturing a chip package, a chip package and chip arrangements Jan 6, 2015 Issued
Array ( [id] => 10597563 [patent_doc_number] => 09318660 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-04-19 [patent_title] => 'Methods of growing nitride semiconductors and methods of manufacturing nitride semiconductor substrates' [patent_app_type] => utility [patent_app_number] => 14/590548 [patent_app_country] => US [patent_app_date] => 2015-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 6365 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14590548 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/590548
Methods of growing nitride semiconductors and methods of manufacturing nitride semiconductor substrates Jan 5, 2015 Issued
Array ( [id] => 10993302 [patent_doc_number] => 20160190248 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-06-30 [patent_title] => 'TRANSISTOR STRUCTURE WITH REDUCED PARASITIC SIDE WALL CHARACTERISTICS' [patent_app_type] => utility [patent_app_number] => 14/585211 [patent_app_country] => US [patent_app_date] => 2014-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 10023 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14585211 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/585211
Transistor structure with reduced parasitic side wall characteristics Dec 29, 2014 Issued
Array ( [id] => 10302817 [patent_doc_number] => 20150187817 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-07-02 [patent_title] => 'LIQUID CRYSTAL DISPLAY DEVICE AND MANUFACTURING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 14/584958 [patent_app_country] => US [patent_app_date] => 2014-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4308 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14584958 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/584958
Liquid crystal display device and manufacturing method thereof Dec 28, 2014 Issued
Array ( [id] => 10214324 [patent_doc_number] => 20150099316 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-04-09 [patent_title] => 'METHOD OF FORMING METALLIC BONDING LAYER AND METHOD OF MANUFACTURING SEMICONDUCTOR LIGHT EMITTING DEVICE USING THE SAME' [patent_app_type] => utility [patent_app_number] => 14/569402 [patent_app_country] => US [patent_app_date] => 2014-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 14494 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14569402 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/569402
Method of forming metal bonding layer and method of manufacturing semiconductor light emitting device using the same Dec 11, 2014 Issued
Array ( [id] => 11694717 [patent_doc_number] => 20170170434 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-15 [patent_title] => 'METHOD FOR MANUFACTURING SUBSTRATE, SUBSTRATE, METHOD FOR MANUFACTURING ORGANIC ELECTROLUMINESCENCE DEVICE, AND ORGANIC ELECTROLUMINESCENCE DEVICE' [patent_app_type] => utility [patent_app_number] => 15/039543 [patent_app_country] => US [patent_app_date] => 2014-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 7042 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15039543 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/039543
METHOD FOR MANUFACTURING SUBSTRATE, SUBSTRATE, METHOD FOR MANUFACTURING ORGANIC ELECTROLUMINESCENCE DEVICE, AND ORGANIC ELECTROLUMINESCENCE DEVICE Nov 18, 2014 Abandoned
Array ( [id] => 9917287 [patent_doc_number] => 20150072492 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-03-12 [patent_title] => 'METHOD FOR FABRICATING NON-VOLATILE MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 14/540840 [patent_app_country] => US [patent_app_date] => 2014-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 3544 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14540840 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/540840
Method for fabricating non-volatile memory device Nov 12, 2014 Issued
Array ( [id] => 10247955 [patent_doc_number] => 20150132951 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-05-14 [patent_title] => 'Surface Poisoning Using ALD For High Selectivity Deposition Of High Aspect Ratio Features' [patent_app_type] => utility [patent_app_number] => 14/538292 [patent_app_country] => US [patent_app_date] => 2014-11-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4535 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14538292 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/538292
Surface poisoning using ALD for high selectivity deposition of high aspect ratio features Nov 10, 2014 Issued
Array ( [id] => 10053591 [patent_doc_number] => 09093477 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-07-28 [patent_title] => 'Implantation processing step for a recess in finFET' [patent_app_type] => utility [patent_app_number] => 14/536674 [patent_app_country] => US [patent_app_date] => 2014-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 3692 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14536674 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/536674
Implantation processing step for a recess in finFET Nov 8, 2014 Issued
Array ( [id] => 10249304 [patent_doc_number] => 20150134300 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-05-14 [patent_title] => 'TEXTURE ANALYSIS OF A COATED SURFACE USING PIVOT-NORMALIZATION' [patent_app_type] => utility [patent_app_number] => 14/535380 [patent_app_country] => US [patent_app_date] => 2014-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3022 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14535380 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/535380
Texture analysis of a coated surface using pivot-normalization Nov 6, 2014 Issued
Array ( [id] => 10247943 [patent_doc_number] => 20150132939 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-05-14 [patent_title] => 'METHOD FOR DEPOSITING METAL LAYERS ON GERMANIUM-CONTAINING FILMS USING METAL CHLORIDE PRECURSORS' [patent_app_type] => utility [patent_app_number] => 14/534496 [patent_app_country] => US [patent_app_date] => 2014-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3499 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14534496 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/534496
Method for depositing metal layers on germanium-containing films using metal chloride precursors Nov 5, 2014 Issued
Array ( [id] => 10073448 [patent_doc_number] => 09111812 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-08-18 [patent_title] => 'Method of manufacturing flexible display device' [patent_app_type] => utility [patent_app_number] => 14/531574 [patent_app_country] => US [patent_app_date] => 2014-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 3450 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14531574 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/531574
Method of manufacturing flexible display device Nov 2, 2014 Issued
Array ( [id] => 10022256 [patent_doc_number] => 09064749 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-06-23 [patent_title] => 'Array substrate' [patent_app_type] => utility [patent_app_number] => 14/526460 [patent_app_country] => US [patent_app_date] => 2014-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5720 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14526460 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/526460
Array substrate Oct 27, 2014 Issued
Array ( [id] => 10770483 [patent_doc_number] => 20160116639 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-04-28 [patent_title] => 'APPARATUS, SYSTEM AND METHOD TO MITIGATE RISK OF ADVERSE OPERATIONAL ENVIRONMENTAL EFFECTS' [patent_app_type] => utility [patent_app_number] => 14/523613 [patent_app_country] => US [patent_app_date] => 2014-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3058 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14523613 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/523613
APPARATUS, SYSTEM AND METHOD TO MITIGATE RISK OF ADVERSE OPERATIONAL ENVIRONMENTAL EFFECTS Oct 23, 2014 Abandoned
Array ( [id] => 10502455 [patent_doc_number] => 09230857 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-01-05 [patent_title] => 'Method to improve semiconductor surfaces and polishing' [patent_app_type] => utility [patent_app_number] => 14/522011 [patent_app_country] => US [patent_app_date] => 2014-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 19 [patent_no_of_words] => 5301 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14522011 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/522011
Method to improve semiconductor surfaces and polishing Oct 22, 2014 Issued
Array ( [id] => 9836348 [patent_doc_number] => 20150028429 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-01-29 [patent_title] => 'SEMICONDUCTOR DEVICE WITH REDUCED DEFECTS' [patent_app_type] => utility [patent_app_number] => 14/514956 [patent_app_country] => US [patent_app_date] => 2014-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3539 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14514956 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/514956
Semiconductor device with reduced defects Oct 14, 2014 Issued
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