Search

Alexander G. Ghyka

Examiner (ID: 13103, Phone: (571)272-1669 , Office: P/2812 )

Most Active Art Unit
2812
Art Unit(s)
2812, 1106, 1754, 1105, 2899
Total Applications
3009
Issued Applications
2443
Pending Applications
238
Abandoned Applications
365

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 10466214 [patent_doc_number] => 20150351229 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-12-03 [patent_title] => 'PRINTED CIRCUIT BOARD COMPRISING CO-PLANAR SURFACE PADS AND INSULATING DIELECTRIC' [patent_app_type] => utility [patent_app_number] => 14/289098 [patent_app_country] => US [patent_app_date] => 2014-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3080 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14289098 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/289098
PRINTED CIRCUIT BOARD COMPRISING CO-PLANAR SURFACE PADS AND INSULATING DIELECTRIC May 27, 2014 Abandoned
Array ( [id] => 9697031 [patent_doc_number] => 20140246716 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-09-04 [patent_title] => 'MULTI-TIERED SEMICONDUCTOR DEVICES AND ASSOCIATED METHODS' [patent_app_type] => utility [patent_app_number] => 14/274933 [patent_app_country] => US [patent_app_date] => 2014-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 4286 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14274933 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/274933
Multi-tiered semiconductor devices and associated methods May 11, 2014 Issued
Array ( [id] => 9686016 [patent_doc_number] => 20140242781 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-08-28 [patent_title] => 'COATING ADHESIVES ONTO DICING BEFORE GRINDING AND MICRO-FABRICATED WAFERS' [patent_app_type] => utility [patent_app_number] => 14/270886 [patent_app_country] => US [patent_app_date] => 2014-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3245 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14270886 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/270886
Coating adhesives onto dicing before grinding and micro-fabricated wafers May 5, 2014 Issued
Array ( [id] => 9682620 [patent_doc_number] => 20140239383 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-08-28 [patent_title] => 'WAFER LEVEL CHIP SCALE PACKAGE AND PROCESS OF MANUFACTURE' [patent_app_type] => utility [patent_app_number] => 14/271168 [patent_app_country] => US [patent_app_date] => 2014-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 3421 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14271168 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/271168
Wafer level chip scale package and process of manufacture May 5, 2014 Issued
Array ( [id] => 9668036 [patent_doc_number] => 20140231899 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-08-21 [patent_title] => 'METHODS OF MANUFACTURING THREE-DIMENSIONAL SEMICONDUCTOR DEVICES' [patent_app_type] => utility [patent_app_number] => 14/265959 [patent_app_country] => US [patent_app_date] => 2014-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 30 [patent_no_of_words] => 13661 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14265959 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/265959
METHODS OF MANUFACTURING THREE-DIMENSIONAL SEMICONDUCTOR DEVICES Apr 29, 2014 Abandoned
Array ( [id] => 13950555 [patent_doc_number] => 10211056 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-02-19 [patent_title] => Semiconductor device manufacturing method [patent_app_type] => utility [patent_app_number] => 15/116617 [patent_app_country] => US [patent_app_date] => 2014-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 3274 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15116617 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/116617
Semiconductor device manufacturing method Apr 24, 2014 Issued
Array ( [id] => 10740805 [patent_doc_number] => 20160086956 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-03-24 [patent_title] => 'SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 14/787964 [patent_app_country] => US [patent_app_date] => 2014-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7518 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14787964 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/787964
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE Apr 15, 2014 Abandoned
Array ( [id] => 11831961 [patent_doc_number] => 09728711 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-08-08 [patent_title] => 'Thermally-assisted MRAM cells with improved reliability at writing' [patent_app_type] => utility [patent_app_number] => 14/787957 [patent_app_country] => US [patent_app_date] => 2014-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2862 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 215 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14787957 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/787957
Thermally-assisted MRAM cells with improved reliability at writing Apr 10, 2014 Issued
Array ( [id] => 9616325 [patent_doc_number] => 20140206182 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-07-24 [patent_title] => 'METHODS AND DEVICES FOR FORMING NANOSTRUCTURE MONOLAYERS AND DEVICES INCLUDING SUCH MONOLAYERS' [patent_app_type] => utility [patent_app_number] => 14/251092 [patent_app_country] => US [patent_app_date] => 2014-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 21133 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14251092 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/251092
Methods and devices for forming nanostructure monolayers and devices including such monolayers Apr 10, 2014 Issued
Array ( [id] => 10022421 [patent_doc_number] => 09064916 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-06-23 [patent_title] => 'Heat treatment method and heat treatment apparatus' [patent_app_type] => utility [patent_app_number] => 14/250131 [patent_app_country] => US [patent_app_date] => 2014-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 24 [patent_no_of_words] => 15307 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 300 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14250131 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/250131
Heat treatment method and heat treatment apparatus Apr 9, 2014 Issued
Array ( [id] => 10402594 [patent_doc_number] => 20150287604 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-10-08 [patent_title] => 'METHODS OF CROSS-COUPLING LINE SEGMENTS ON A WAFER' [patent_app_type] => utility [patent_app_number] => 14/246197 [patent_app_country] => US [patent_app_date] => 2014-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4667 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14246197 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/246197
Methods of cross-coupling line segments on a wafer Apr 6, 2014 Issued
Array ( [id] => 10544680 [patent_doc_number] => 09269817 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-02-23 [patent_title] => 'Semiconductor device and manufacturing method thereof, delamination method, and transferring method' [patent_app_type] => utility [patent_app_number] => 14/223419 [patent_app_country] => US [patent_app_date] => 2014-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 71 [patent_no_of_words] => 9617 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14223419 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/223419
Semiconductor device and manufacturing method thereof, delamination method, and transferring method Mar 23, 2014 Issued
Array ( [id] => 10131971 [patent_doc_number] => 09165812 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-10-20 [patent_title] => 'Cooled tape frame lift and low contact shadow ring for plasma heat isolation' [patent_app_type] => utility [patent_app_number] => 14/219851 [patent_app_country] => US [patent_app_date] => 2014-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 25 [patent_no_of_words] => 15273 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 208 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14219851 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/219851
Cooled tape frame lift and low contact shadow ring for plasma heat isolation Mar 18, 2014 Issued
Array ( [id] => 10131971 [patent_doc_number] => 09165812 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-10-20 [patent_title] => 'Cooled tape frame lift and low contact shadow ring for plasma heat isolation' [patent_app_type] => utility [patent_app_number] => 14/219851 [patent_app_country] => US [patent_app_date] => 2014-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 25 [patent_no_of_words] => 15273 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 208 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14219851 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/219851
Cooled tape frame lift and low contact shadow ring for plasma heat isolation Mar 18, 2014 Issued
Array ( [id] => 9737586 [patent_doc_number] => 20140273304 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-09-18 [patent_title] => 'METHODS FOR REDUCING ETCH NONUNIFORMITY IN THE PRESENCE OF A WEAK MAGNETIC FIELD IN AN INDUCTIVELY COUPLED PLASMA REACTOR' [patent_app_type] => utility [patent_app_number] => 14/206723 [patent_app_country] => US [patent_app_date] => 2014-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3705 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14206723 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/206723
Methods for reducing etch nonuniformity in the presence of a weak magnetic field in an inductively coupled plasma reactor Mar 11, 2014 Issued
Array ( [id] => 11831651 [patent_doc_number] => 09728401 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-08-08 [patent_title] => 'Methods for conformal treatment of dielectric films with low thermal budget' [patent_app_type] => utility [patent_app_number] => 14/206766 [patent_app_country] => US [patent_app_date] => 2014-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3166 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14206766 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/206766
Methods for conformal treatment of dielectric films with low thermal budget Mar 11, 2014 Issued
Array ( [id] => 9737808 [patent_doc_number] => 20140273526 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-09-18 [patent_title] => 'Atomic Layer Deposition Of Films Comprising Si(C)N Using Hydrazine, Azide And/Or Silyl Amine Derivatives' [patent_app_type] => utility [patent_app_number] => 14/205921 [patent_app_country] => US [patent_app_date] => 2014-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6443 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14205921 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/205921
Atomic Layer Deposition Of Films Comprising Si(C)N Using Hydrazine, Azide And/Or Silyl Amine Derivatives Mar 11, 2014 Abandoned
Array ( [id] => 10531153 [patent_doc_number] => 09257293 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-02-09 [patent_title] => 'Methods of forming silicon nitride spacers' [patent_app_type] => utility [patent_app_number] => 14/205673 [patent_app_country] => US [patent_app_date] => 2014-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 4277 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14205673 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/205673
Methods of forming silicon nitride spacers Mar 11, 2014 Issued
Array ( [id] => 10624351 [patent_doc_number] => 09343301 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-05-17 [patent_title] => 'Quantum dots made using phosphine' [patent_app_type] => utility [patent_app_number] => 14/207084 [patent_app_country] => US [patent_app_date] => 2014-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 9147 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14207084 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/207084
Quantum dots made using phosphine Mar 11, 2014 Issued
Array ( [id] => 9737599 [patent_doc_number] => 20140273318 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-09-18 [patent_title] => 'METHOD OF FORMING METALLIC BONDING LAYER AND METHOD OF MANUFACTURING SEMICONDUCTOR LIGHT EMITTING DEVICE THEREWITH' [patent_app_type] => utility [patent_app_number] => 14/207466 [patent_app_country] => US [patent_app_date] => 2014-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 9588 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14207466 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/207466
METHOD OF FORMING METALLIC BONDING LAYER AND METHOD OF MANUFACTURING SEMICONDUCTOR LIGHT EMITTING DEVICE THEREWITH Mar 11, 2014 Abandoned
Menu