Search

Alexander G. Ghyka

Examiner (ID: 13178, Phone: (571)272-1669 , Office: P/2812 )

Most Active Art Unit
2812
Art Unit(s)
1754, 1106, 2812, 1105, 2899
Total Applications
3016
Issued Applications
2445
Pending Applications
242
Abandoned Applications
365

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 9191557 [patent_doc_number] => 20130330872 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-12-12 [patent_title] => 'ION IMPLANTATION FABRICATION PROCESS FOR THIN-FILM CRYSTALLINE SILICON SOLAR CELLS' [patent_app_type] => utility [patent_app_number] => 13/688062 [patent_app_country] => US [patent_app_date] => 2012-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 7224 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13688062 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/688062
ION IMPLANTATION FABRICATION PROCESS FOR THIN-FILM CRYSTALLINE SILICON SOLAR CELLS Nov 27, 2012 Abandoned
Array ( [id] => 8853677 [patent_doc_number] => 20130143352 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-06-06 [patent_title] => 'PHOTOVOLTAIC DEVICES INCLUDING MG-DOPED SEMICONDUCTOR FILMS' [patent_app_type] => utility [patent_app_number] => 13/685035 [patent_app_country] => US [patent_app_date] => 2012-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4009 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13685035 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/685035
Photovoltaic devices including MG-doped semiconductor films Nov 25, 2012 Issued
Array ( [id] => 10570187 [patent_doc_number] => 09293364 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-03-22 [patent_title] => 'Electroless plating apparatus and electroless plating method' [patent_app_type] => utility [patent_app_number] => 13/677388 [patent_app_country] => US [patent_app_date] => 2012-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 37 [patent_figures_cnt] => 51 [patent_no_of_words] => 19984 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13677388 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/677388
Electroless plating apparatus and electroless plating method Nov 14, 2012 Issued
Array ( [id] => 9031624 [patent_doc_number] => 20130234262 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-09-12 [patent_title] => 'SEMICONDUCTOR DEVICE AND FABRICATION METHOD' [patent_app_type] => utility [patent_app_number] => 13/672696 [patent_app_country] => US [patent_app_date] => 2012-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3539 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13672696 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/672696
Semiconductor device and fabrication method Nov 7, 2012 Issued
Array ( [id] => 9944122 [patent_doc_number] => 08993422 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-03-31 [patent_title] => 'Process tools and methods of forming devices using process tools' [patent_app_type] => utility [patent_app_number] => 13/670402 [patent_app_country] => US [patent_app_date] => 2012-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 27 [patent_no_of_words] => 5824 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13670402 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/670402
Process tools and methods of forming devices using process tools Nov 5, 2012 Issued
Array ( [id] => 8697062 [patent_doc_number] => 20130059071 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-03-07 [patent_title] => 'LOW CONTAMINATION COMPONENTS FOR SEMICONDUCTOR PROCESSSING APPARATUS AND METHODS FOR MAKING COMPONENTS' [patent_app_type] => utility [patent_app_number] => 13/667911 [patent_app_country] => US [patent_app_date] => 2012-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7591 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 29 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13667911 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/667911
LOW CONTAMINATION COMPONENTS FOR SEMICONDUCTOR PROCESSSING APPARATUS AND METHODS FOR MAKING COMPONENTS Nov 1, 2012 Abandoned
Array ( [id] => 9865963 [patent_doc_number] => 20150045982 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-02-12 [patent_title] => 'Method and System for Defining a Selection Range for a Variable Speed Device' [patent_app_type] => utility [patent_app_number] => 14/374858 [patent_app_country] => US [patent_app_date] => 2012-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 9670 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14374858 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/374858
Method and System for Defining a Selection Range for a Variable Speed Device Oct 31, 2012 Abandoned
Array ( [id] => 10590542 [patent_doc_number] => 09312162 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-04-12 [patent_title] => 'Dicing sheet and a production method of a semiconductor chip' [patent_app_type] => utility [patent_app_number] => 13/665972 [patent_app_country] => US [patent_app_date] => 2012-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 9633 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13665972 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/665972
Dicing sheet and a production method of a semiconductor chip Oct 31, 2012 Issued
Array ( [id] => 9107755 [patent_doc_number] => 20130280887 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-10-24 [patent_title] => 'Method For Releasing a Thin-Film Substrate' [patent_app_type] => utility [patent_app_number] => 13/657718 [patent_app_country] => US [patent_app_date] => 2012-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 10636 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13657718 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/657718
Method For Releasing a Thin-Film Substrate Oct 21, 2012 Abandoned
Array ( [id] => 10336763 [patent_doc_number] => 20150221768 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-08-06 [patent_title] => 'SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 14/423132 [patent_app_country] => US [patent_app_date] => 2012-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 4213 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14423132 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/423132
SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME Sep 16, 2012 Abandoned
Array ( [id] => 8606656 [patent_doc_number] => 20130011968 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-01-10 [patent_title] => 'HYBRID BONDING TECHNIQUES FOR MULTI-LAYER SEMICONDUCTOR STACKS' [patent_app_type] => utility [patent_app_number] => 13/618656 [patent_app_country] => US [patent_app_date] => 2012-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 12138 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13618656 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/618656
HYBRID BONDING TECHNIQUES FOR MULTI-LAYER SEMICONDUCTOR STACKS Sep 13, 2012 Abandoned
Array ( [id] => 9530086 [patent_doc_number] => 08753959 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-06-17 [patent_title] => 'Coating adhesives onto dicing before grinding and micro-fabricated wafers' [patent_app_type] => utility [patent_app_number] => 13/613142 [patent_app_country] => US [patent_app_date] => 2012-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3225 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13613142 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/613142
Coating adhesives onto dicing before grinding and micro-fabricated wafers Sep 12, 2012 Issued
Array ( [id] => 9153535 [patent_doc_number] => 08586441 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-11-19 [patent_title] => 'Germanium lateral bipolar junction transistor' [patent_app_type] => utility [patent_app_number] => 13/611606 [patent_app_country] => US [patent_app_date] => 2012-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8205 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13611606 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/611606
Germanium lateral bipolar junction transistor Sep 11, 2012 Issued
Array ( [id] => 8617447 [patent_doc_number] => 20130022759 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-01-24 [patent_title] => 'PLASMA PROCESSING METHOD AND APPARATUS' [patent_app_type] => utility [patent_app_number] => 13/611939 [patent_app_country] => US [patent_app_date] => 2012-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 17251 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13611939 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/611939
Plasma processing method and apparatus Sep 11, 2012 Issued
Array ( [id] => 9239104 [patent_doc_number] => 08603895 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-12-10 [patent_title] => 'Methods of forming isolation structures for semiconductor devices by performing a deposition-etch-deposition sequence' [patent_app_type] => utility [patent_app_number] => 13/610263 [patent_app_country] => US [patent_app_date] => 2012-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 4378 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13610263 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/610263
Methods of forming isolation structures for semiconductor devices by performing a deposition-etch-deposition sequence Sep 10, 2012 Issued
Array ( [id] => 9360504 [patent_doc_number] => 20140070376 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-03-13 [patent_title] => 'Methods for manufacturing a chip arrangement, methods for manufacturing a chip package, a chip package and chip arrangements' [patent_app_type] => utility [patent_app_number] => 13/609306 [patent_app_country] => US [patent_app_date] => 2012-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 7530 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13609306 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/609306
Methods for manufacturing a chip arrangement, methods for manufacturing a chip package, a chip package and chip arrangements Sep 10, 2012 Issued
Array ( [id] => 8780156 [patent_doc_number] => 20130102131 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-04-25 [patent_title] => 'METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 13/610032 [patent_app_country] => US [patent_app_date] => 2012-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 7539 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13610032 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/610032
METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE Sep 10, 2012 Abandoned
Array ( [id] => 9817582 [patent_doc_number] => 08927366 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-01-06 [patent_title] => 'Method of manufacturing a non-volatile memory device having a vertical structure' [patent_app_type] => utility [patent_app_number] => 13/610344 [patent_app_country] => US [patent_app_date] => 2012-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 28 [patent_no_of_words] => 11817 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13610344 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/610344
Method of manufacturing a non-volatile memory device having a vertical structure Sep 10, 2012 Issued
Array ( [id] => 9205501 [patent_doc_number] => 20140004678 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-01-02 [patent_title] => 'METHOD FOR FABRICATING CAPACITOR OF SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 13/610588 [patent_app_country] => US [patent_app_date] => 2012-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3368 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13610588 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/610588
Method for fabricating capacitor of semiconductor device Sep 10, 2012 Issued
Array ( [id] => 8582867 [patent_doc_number] => 20130001688 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-01-03 [patent_title] => 'SELF-ALIGNED BODY FULLY ISOLATED DEVICE' [patent_app_type] => utility [patent_app_number] => 13/609270 [patent_app_country] => US [patent_app_date] => 2012-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 11477 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13609270 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/609270
Self-aligned body fully isolated device Sep 10, 2012 Issued
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