Search

Alexander Marion Weddle

Examiner (ID: 434, Phone: (571)270-5346 , Office: P/1712 )

Most Active Art Unit
1712
Art Unit(s)
1792, 1712, 1714
Total Applications
1047
Issued Applications
604
Pending Applications
117
Abandoned Applications
365

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4195262 [patent_doc_number] => 06085313 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-04 [patent_title] => 'Computer processor system for executing RXE format floating point instructions' [patent_app_type] => 1 [patent_app_number] => 9/070198 [patent_app_country] => US [patent_app_date] => 1998-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 1937 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 304 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/085/06085313.pdf [firstpage_image] =>[orig_patent_app_number] => 070198 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/070198
Computer processor system for executing RXE format floating point instructions Apr 29, 1998 Issued
Array ( [id] => 3945143 [patent_doc_number] => 05935235 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-10 [patent_title] => 'Method for branching to an instruction in a computer program at a memory address pointed to by a key in a data structure' [patent_app_type] => 1 [patent_app_number] => 9/062787 [patent_app_country] => US [patent_app_date] => 1998-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 9043 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/935/05935235.pdf [firstpage_image] =>[orig_patent_app_number] => 062787 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/062787
Method for branching to an instruction in a computer program at a memory address pointed to by a key in a data structure Apr 15, 1998 Issued
Array ( [id] => 4116335 [patent_doc_number] => 06067617 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-23 [patent_title] => 'Specialized millicode instructions for packed decimal division' [patent_app_type] => 1 [patent_app_number] => 9/056486 [patent_app_country] => US [patent_app_date] => 1998-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 10 [patent_no_of_words] => 8047 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 366 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/067/06067617.pdf [firstpage_image] =>[orig_patent_app_number] => 056486 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/056486
Specialized millicode instructions for packed decimal division Apr 6, 1998 Issued
Array ( [id] => 7642366 [patent_doc_number] => 06430680 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-06 [patent_title] => 'Processor and method of prefetching data based upon a detected stride' [patent_app_type] => B1 [patent_app_number] => 09/052567 [patent_app_country] => US [patent_app_date] => 1998-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3259 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 6 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/430/06430680.pdf [firstpage_image] =>[orig_patent_app_number] => 09052567 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/052567
Processor and method of prefetching data based upon a detected stride Mar 30, 1998 Issued
Array ( [id] => 1572003 [patent_doc_number] => 06377970 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-23 [patent_title] => 'Method and apparatus for computing a sum of packed data elements using SIMD multiply circuitry' [patent_app_type] => B1 [patent_app_number] => 09/052904 [patent_app_country] => US [patent_app_date] => 1998-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 7920 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/377/06377970.pdf [firstpage_image] =>[orig_patent_app_number] => 09052904 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/052904
Method and apparatus for computing a sum of packed data elements using SIMD multiply circuitry Mar 30, 1998 Issued
Array ( [id] => 4118475 [patent_doc_number] => 06098168 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-01 [patent_title] => 'System for completing instruction out-of-order which performs target address comparisons prior to dispatch' [patent_app_type] => 1 [patent_app_number] => 9/046867 [patent_app_country] => US [patent_app_date] => 1998-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4283 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/098/06098168.pdf [firstpage_image] =>[orig_patent_app_number] => 046867 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/046867
System for completing instruction out-of-order which performs target address comparisons prior to dispatch Mar 23, 1998 Issued
Array ( [id] => 4162549 [patent_doc_number] => 06032246 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-29 [patent_title] => 'Bit-slice processing unit having M CPU\'s reading an N-bit width data element stored bit-sliced across M memories' [patent_app_type] => 1 [patent_app_number] => 9/045863 [patent_app_country] => US [patent_app_date] => 1998-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 14 [patent_no_of_words] => 9580 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/032/06032246.pdf [firstpage_image] =>[orig_patent_app_number] => 045863 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/045863
Bit-slice processing unit having M CPU's reading an N-bit width data element stored bit-sliced across M memories Mar 22, 1998 Issued
Array ( [id] => 4199209 [patent_doc_number] => 06038651 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-14 [patent_title] => 'SMP clusters with remote resource managers for distributing work to other clusters while reducing bus traffic to a minimum' [patent_app_type] => 1 [patent_app_number] => 9/046430 [patent_app_country] => US [patent_app_date] => 1998-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 15318 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/038/06038651.pdf [firstpage_image] =>[orig_patent_app_number] => 046430 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/046430
SMP clusters with remote resource managers for distributing work to other clusters while reducing bus traffic to a minimum Mar 22, 1998 Issued
Array ( [id] => 1557628 [patent_doc_number] => 06401200 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-04 [patent_title] => 'Device for simultaneously downloading code into plural DSP memories from single master memory' [patent_app_type] => B1 [patent_app_number] => 09/044437 [patent_app_country] => US [patent_app_date] => 1998-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 19 [patent_no_of_words] => 5899 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/401/06401200.pdf [firstpage_image] =>[orig_patent_app_number] => 09044437 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/044437
Device for simultaneously downloading code into plural DSP memories from single master memory Mar 18, 1998 Issued
09/044104 HIGHLY PARALLEL VARIABLE LENGTH INSTRUCTIONS FOR CONTROLLING A DIGITAL SIGNAL PROCESSOR Mar 17, 1998 Abandoned
Array ( [id] => 1444124 [patent_doc_number] => 06496920 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-17 [patent_title] => 'Digital signal processor having multiple access registers' [patent_app_type] => B1 [patent_app_number] => 09/044088 [patent_app_country] => US [patent_app_date] => 1998-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 15869 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/496/06496920.pdf [firstpage_image] =>[orig_patent_app_number] => 09044088 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/044088
Digital signal processor having multiple access registers Mar 17, 1998 Issued
Array ( [id] => 4176888 [patent_doc_number] => 06157997 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-05 [patent_title] => 'Processor and information processing apparatus with a reconfigurable circuit' [patent_app_type] => 1 [patent_app_number] => 9/038834 [patent_app_country] => US [patent_app_date] => 1998-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 2916 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/157/06157997.pdf [firstpage_image] =>[orig_patent_app_number] => 038834 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/038834
Processor and information processing apparatus with a reconfigurable circuit Mar 11, 1998 Issued
Array ( [id] => 4257866 [patent_doc_number] => 06145076 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-07 [patent_title] => 'System for executing nested software loops with tracking of loop nesting level' [patent_app_type] => 1 [patent_app_number] => 9/037445 [patent_app_country] => US [patent_app_date] => 1998-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 5604 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/145/06145076.pdf [firstpage_image] =>[orig_patent_app_number] => 037445 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/037445
System for executing nested software loops with tracking of loop nesting level Mar 9, 1998 Issued
Array ( [id] => 4177507 [patent_doc_number] => 06105129 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-15 [patent_title] => 'Converting register data from a first format type to a second format type if a second type instruction consumes data produced by a first type instruction' [patent_app_type] => 1 [patent_app_number] => 9/025233 [patent_app_country] => US [patent_app_date] => 1998-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 15771 [patent_no_of_claims] => 49 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/105/06105129.pdf [firstpage_image] =>[orig_patent_app_number] => 025233 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/025233
Converting register data from a first format type to a second format type if a second type instruction consumes data produced by a first type instruction Feb 17, 1998 Issued
Array ( [id] => 1557344 [patent_doc_number] => 06349379 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-02-19 [patent_title] => 'System for executing instructions having flag for indicating direct or indirect specification of a length of operand data' [patent_app_type] => B2 [patent_app_number] => 09/025194 [patent_app_country] => US [patent_app_date] => 1998-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 135 [patent_figures_cnt] => 166 [patent_no_of_words] => 69372 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/349/06349379.pdf [firstpage_image] =>[orig_patent_app_number] => 09025194 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/025194
System for executing instructions having flag for indicating direct or indirect specification of a length of operand data Feb 17, 1998 Issued
Array ( [id] => 4152860 [patent_doc_number] => 06148394 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-14 [patent_title] => 'Apparatus and method for tracking out of order load instructions to avoid data coherency violations in a processor' [patent_app_type] => 1 [patent_app_number] => 9/021134 [patent_app_country] => US [patent_app_date] => 1998-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 14 [patent_no_of_words] => 4794 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/148/06148394.pdf [firstpage_image] =>[orig_patent_app_number] => 021134 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/021134
Apparatus and method for tracking out of order load instructions to avoid data coherency violations in a processor Feb 9, 1998 Issued
Array ( [id] => 4206890 [patent_doc_number] => 06131157 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-10 [patent_title] => 'System and method for retiring approximately simultaneously a group of instructions in a superscalar microprocessor' [patent_app_type] => 1 [patent_app_number] => 9/009412 [patent_app_country] => US [patent_app_date] => 1998-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 6696 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/131/06131157.pdf [firstpage_image] =>[orig_patent_app_number] => 009412 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/009412
System and method for retiring approximately simultaneously a group of instructions in a superscalar microprocessor Jan 19, 1998 Issued
Array ( [id] => 1132574 [patent_doc_number] => 06792256 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-09-14 [patent_title] => 'Antenna connectors for computer devices utilizing radio and modem cards' [patent_app_type] => B1 [patent_app_number] => 09/006566 [patent_app_country] => US [patent_app_date] => 1998-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 31 [patent_no_of_words] => 6679 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/792/06792256.pdf [firstpage_image] =>[orig_patent_app_number] => 09006566 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/006566
Antenna connectors for computer devices utilizing radio and modem cards Jan 12, 1998 Issued
Array ( [id] => 4168638 [patent_doc_number] => 06157465 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-05 [patent_title] => 'System for transferring jobs between processing units based upon content of job and ability of unit to perform job' [patent_app_type] => 1 [patent_app_number] => 8/998928 [patent_app_country] => US [patent_app_date] => 1997-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 112 [patent_figures_cnt] => 134 [patent_no_of_words] => 31544 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 261 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/157/06157465.pdf [firstpage_image] =>[orig_patent_app_number] => 998928 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/998928
System for transferring jobs between processing units based upon content of job and ability of unit to perform job Dec 28, 1997 Issued
Array ( [id] => 4179424 [patent_doc_number] => 06115807 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-05 [patent_title] => 'Static instruction decoder utilizing a circular queue to decode instructions and select instructions to be issued' [patent_app_type] => 1 [patent_app_number] => 8/994516 [patent_app_country] => US [patent_app_date] => 1997-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4389 [patent_no_of_claims] => 41 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/115/06115807.pdf [firstpage_image] =>[orig_patent_app_number] => 994516 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/994516
Static instruction decoder utilizing a circular queue to decode instructions and select instructions to be issued Dec 18, 1997 Issued
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