Search

Alexander Marion Weddle

Examiner (ID: 434, Phone: (571)270-5346 , Office: P/1712 )

Most Active Art Unit
1712
Art Unit(s)
1792, 1712, 1714
Total Applications
1047
Issued Applications
604
Pending Applications
117
Abandoned Applications
365

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4257186 [patent_doc_number] => 06081888 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-27 [patent_title] => 'Adaptive microprocessor with dynamically reconfigurable microcode responsive to external signals to initiate microcode reloading' [patent_app_type] => 1 [patent_app_number] => 8/914609 [patent_app_country] => US [patent_app_date] => 1997-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1861 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/081/06081888.pdf [firstpage_image] =>[orig_patent_app_number] => 914609 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/914609
Adaptive microprocessor with dynamically reconfigurable microcode responsive to external signals to initiate microcode reloading Aug 20, 1997 Issued
Array ( [id] => 3997812 [patent_doc_number] => 05949973 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-07 [patent_title] => 'Method of relocating the stack in a computer system for preventing overrate by an exploit program' [patent_app_type] => 1 [patent_app_number] => 8/900518 [patent_app_country] => US [patent_app_date] => 1997-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 6178 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/949/05949973.pdf [firstpage_image] =>[orig_patent_app_number] => 900518 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/900518
Method of relocating the stack in a computer system for preventing overrate by an exploit program Jul 24, 1997 Issued
Array ( [id] => 4031512 [patent_doc_number] => 05881280 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-09 [patent_title] => 'Method and system for selecting instructions for re-execution for in-line exception recovery in a speculative execution processor' [patent_app_type] => 1 [patent_app_number] => 8/900274 [patent_app_country] => US [patent_app_date] => 1997-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 7988 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/881/05881280.pdf [firstpage_image] =>[orig_patent_app_number] => 900274 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/900274
Method and system for selecting instructions for re-execution for in-line exception recovery in a speculative execution processor Jul 24, 1997 Issued
Array ( [id] => 3983753 [patent_doc_number] => 05887137 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-23 [patent_title] => 'Data processing apparatus having a sorting unit to provide sorted data to a processor' [patent_app_type] => 1 [patent_app_number] => 8/900473 [patent_app_country] => US [patent_app_date] => 1997-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 4954 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/887/05887137.pdf [firstpage_image] =>[orig_patent_app_number] => 900473 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/900473
Data processing apparatus having a sorting unit to provide sorted data to a processor Jul 24, 1997 Issued
Array ( [id] => 4252640 [patent_doc_number] => 06076156 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-13 [patent_title] => 'Instruction redefinition using model specific registers' [patent_app_type] => 1 [patent_app_number] => 8/895800 [patent_app_country] => US [patent_app_date] => 1997-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 7022 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/076/06076156.pdf [firstpage_image] =>[orig_patent_app_number] => 895800 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/895800
Instruction redefinition using model specific registers Jul 16, 1997 Issued
Array ( [id] => 4239180 [patent_doc_number] => 06088782 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-11 [patent_title] => 'Method and apparatus for moving data in a parallel processor using source and destination vector registers' [patent_app_type] => 1 [patent_app_number] => 8/891228 [patent_app_country] => US [patent_app_date] => 1997-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 3787 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/088/06088782.pdf [firstpage_image] =>[orig_patent_app_number] => 891228 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/891228
Method and apparatus for moving data in a parallel processor using source and destination vector registers Jul 9, 1997 Issued
Array ( [id] => 4057549 [patent_doc_number] => 05996059 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-30 [patent_title] => 'System for monitoring an execution pipeline utilizing an address pipeline in parallel with the execution pipeline' [patent_app_type] => 1 [patent_app_number] => 8/886520 [patent_app_country] => US [patent_app_date] => 1997-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4521 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/996/05996059.pdf [firstpage_image] =>[orig_patent_app_number] => 886520 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/886520
System for monitoring an execution pipeline utilizing an address pipeline in parallel with the execution pipeline Jun 30, 1997 Issued
Array ( [id] => 3956631 [patent_doc_number] => 05955898 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-21 [patent_title] => 'Selector and decision wait using pass gate XOR' [patent_app_type] => 1 [patent_app_number] => 8/885169 [patent_app_country] => US [patent_app_date] => 1997-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 5029 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 544 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/955/05955898.pdf [firstpage_image] =>[orig_patent_app_number] => 885169 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/885169
Selector and decision wait using pass gate XOR Jun 29, 1997 Issued
Array ( [id] => 3923440 [patent_doc_number] => 05928355 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-27 [patent_title] => 'Apparatus for reducing instruction issue stage stalls through use of a staging register' [patent_app_type] => 1 [patent_app_number] => 8/884272 [patent_app_country] => US [patent_app_date] => 1997-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5643 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/928/05928355.pdf [firstpage_image] =>[orig_patent_app_number] => 884272 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/884272
Apparatus for reducing instruction issue stage stalls through use of a staging register Jun 26, 1997 Issued
Array ( [id] => 4236562 [patent_doc_number] => 06041399 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-21 [patent_title] => 'VLIW system with predicated instruction execution for individual instruction fields' [patent_app_type] => 1 [patent_app_number] => 8/884667 [patent_app_country] => US [patent_app_date] => 1997-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 16 [patent_no_of_words] => 5857 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/041/06041399.pdf [firstpage_image] =>[orig_patent_app_number] => 884667 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/884667
VLIW system with predicated instruction execution for individual instruction fields Jun 26, 1997 Issued
Array ( [id] => 4040662 [patent_doc_number] => 05884070 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-16 [patent_title] => 'Method for processing single precision arithmetic operations in system where two single precision registers are aliased to one double precision register' [patent_app_type] => 1 [patent_app_number] => 8/882172 [patent_app_country] => US [patent_app_date] => 1997-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4893 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/884/05884070.pdf [firstpage_image] =>[orig_patent_app_number] => 882172 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/882172
Method for processing single precision arithmetic operations in system where two single precision registers are aliased to one double precision register Jun 24, 1997 Issued
Array ( [id] => 3918735 [patent_doc_number] => 05898853 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-04-27 [patent_title] => 'Apparatus for enforcing true dependencies in an out-of-order processor' [patent_app_type] => 1 [patent_app_number] => 8/882173 [patent_app_country] => US [patent_app_date] => 1997-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4856 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/898/05898853.pdf [firstpage_image] =>[orig_patent_app_number] => 882173 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/882173
Apparatus for enforcing true dependencies in an out-of-order processor Jun 24, 1997 Issued
Array ( [id] => 3966526 [patent_doc_number] => 05999727 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-07 [patent_title] => 'Method for restraining over-eager load boosting using a dependency color indicator stored in cache with both the load and store instructions' [patent_app_type] => 1 [patent_app_number] => 8/882174 [patent_app_country] => US [patent_app_date] => 1997-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7803 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/999/05999727.pdf [firstpage_image] =>[orig_patent_app_number] => 882174 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/882174
Method for restraining over-eager load boosting using a dependency color indicator stored in cache with both the load and store instructions Jun 24, 1997 Issued
Array ( [id] => 3955193 [patent_doc_number] => 05930491 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-27 [patent_title] => 'Identification of related instructions resulting from external to internal translation by use of common ID field for each group' [patent_app_type] => 1 [patent_app_number] => 8/879451 [patent_app_country] => US [patent_app_date] => 1997-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 7619 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/930/05930491.pdf [firstpage_image] =>[orig_patent_app_number] => 879451 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/879451
Identification of related instructions resulting from external to internal translation by use of common ID field for each group Jun 19, 1997 Issued
08/872480 MODULAR SYSTEM FOR ACCELERATING DATA SEARCHES AND DATA STREAM OPERATIONS Jun 8, 1997 Abandoned
Array ( [id] => 4422354 [patent_doc_number] => 06233670 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-15 [patent_title] => 'Superscalar processor with direct result bypass between execution units having comparators in execution units for comparing operand and result addresses and activating result bypassing' [patent_app_type] => 1 [patent_app_number] => 8/865308 [patent_app_country] => US [patent_app_date] => 1997-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 3975 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 261 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/233/06233670.pdf [firstpage_image] =>[orig_patent_app_number] => 865308 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/865308
Superscalar processor with direct result bypass between execution units having comparators in execution units for comparing operand and result addresses and activating result bypassing May 28, 1997 Issued
Array ( [id] => 4022481 [patent_doc_number] => 05987603 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-16 [patent_title] => 'Apparatus and method for reversing bits using a shifter' [patent_app_type] => 1 [patent_app_number] => 8/845817 [patent_app_country] => US [patent_app_date] => 1997-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4510 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/987/05987603.pdf [firstpage_image] =>[orig_patent_app_number] => 845817 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/845817
Apparatus and method for reversing bits using a shifter Apr 28, 1997 Issued
Array ( [id] => 4065436 [patent_doc_number] => 05870619 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-02-09 [patent_title] => 'Array processor with asynchronous availability of a next SIMD instruction' [patent_app_type] => 1 [patent_app_number] => 8/841007 [patent_app_country] => US [patent_app_date] => 1997-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 29 [patent_no_of_words] => 40426 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 251 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/870/05870619.pdf [firstpage_image] =>[orig_patent_app_number] => 841007 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/841007
Array processor with asynchronous availability of a next SIMD instruction Apr 28, 1997 Issued
Array ( [id] => 3898346 [patent_doc_number] => 05894569 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-04-13 [patent_title] => 'Method and system for back-end gathering of store instructions within a data-processing system' [patent_app_type] => 1 [patent_app_number] => 8/839480 [patent_app_country] => US [patent_app_date] => 1997-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3071 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/894/05894569.pdf [firstpage_image] =>[orig_patent_app_number] => 839480 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/839480
Method and system for back-end gathering of store instructions within a data-processing system Apr 13, 1997 Issued
Array ( [id] => 3923368 [patent_doc_number] => 05928350 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-27 [patent_title] => 'Wide memory architecture vector processor using nxP bits wide memory bus for transferring P n-bit vector operands in one cycle' [patent_app_type] => 1 [patent_app_number] => 8/840178 [patent_app_country] => US [patent_app_date] => 1997-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4620 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/928/05928350.pdf [firstpage_image] =>[orig_patent_app_number] => 840178 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/840178
Wide memory architecture vector processor using nxP bits wide memory bus for transferring P n-bit vector operands in one cycle Apr 10, 1997 Issued
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