Search

Alexander Marion Weddle

Examiner (ID: 434, Phone: (571)270-5346 , Office: P/1712 )

Most Active Art Unit
1712
Art Unit(s)
1792, 1712, 1714
Total Applications
1047
Issued Applications
604
Pending Applications
117
Abandoned Applications
365

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1425461 [patent_doc_number] => 06535985 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-03-18 [patent_title] => 'Data processing apparatus' [patent_app_type] => B1 [patent_app_number] => 09/583168 [patent_app_country] => US [patent_app_date] => 2000-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 38 [patent_no_of_words] => 10240 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 245 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/535/06535985.pdf [firstpage_image] =>[orig_patent_app_number] => 09583168 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/583168
Data processing apparatus May 29, 2000 Issued
Array ( [id] => 1481635 [patent_doc_number] => 06345321 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-02-05 [patent_title] => 'Multiple-mode memory component' [patent_app_type] => B1 [patent_app_number] => 09/577447 [patent_app_country] => US [patent_app_date] => 2000-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 27 [patent_no_of_words] => 30579 [patent_no_of_claims] => 59 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/345/06345321.pdf [firstpage_image] =>[orig_patent_app_number] => 09577447 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/577447
Multiple-mode memory component May 23, 2000 Issued
Array ( [id] => 1248889 [patent_doc_number] => 06678819 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-01-13 [patent_title] => 'Pipeline microprocessor with conditional jump in one clock cycle' [patent_app_type] => B1 [patent_app_number] => 09/564477 [patent_app_country] => US [patent_app_date] => 2000-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 4968 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 325 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/678/06678819.pdf [firstpage_image] =>[orig_patent_app_number] => 09564477 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/564477
Pipeline microprocessor with conditional jump in one clock cycle May 2, 2000 Issued
Array ( [id] => 1155286 [patent_doc_number] => 06779105 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-08-17 [patent_title] => 'Two pipeline stage microprocessor and method for processing an instruction' [patent_app_type] => B1 [patent_app_number] => 09/564098 [patent_app_country] => US [patent_app_date] => 2000-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 6597 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 46 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/779/06779105.pdf [firstpage_image] =>[orig_patent_app_number] => 09564098 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/564098
Two pipeline stage microprocessor and method for processing an instruction May 2, 2000 Issued
Array ( [id] => 1377273 [patent_doc_number] => 06578133 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-06-10 [patent_title] => 'MIMD array of single bit processors for processing logic equations in strict sequential order' [patent_app_type] => B1 [patent_app_number] => 09/512091 [patent_app_country] => US [patent_app_date] => 2000-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 8679 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 200 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/578/06578133.pdf [firstpage_image] =>[orig_patent_app_number] => 09512091 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/512091
MIMD array of single bit processors for processing logic equations in strict sequential order Feb 23, 2000 Issued
Array ( [id] => 6836132 [patent_doc_number] => 20030163678 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-08-28 [patent_title] => 'METHOD AND APPARATUS FOR REDUCING BRANCH PREDICTION TABLE POLLUTION' [patent_app_type] => new [patent_app_number] => 09/507499 [patent_app_country] => US [patent_app_date] => 2000-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3348 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0163/20030163678.pdf [firstpage_image] =>[orig_patent_app_number] => 09507499 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/507499
Method and apparatus for reducing branch prediction table pollution Feb 17, 2000 Issued
Array ( [id] => 1466312 [patent_doc_number] => 06393549 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-21 [patent_title] => 'Instruction alignment unit for routing variable byte-length instructions' [patent_app_type] => B1 [patent_app_number] => 09/468693 [patent_app_country] => US [patent_app_date] => 1999-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 62 [patent_figures_cnt] => 70 [patent_no_of_words] => 73637 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/393/06393549.pdf [firstpage_image] =>[orig_patent_app_number] => 09468693 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/468693
Instruction alignment unit for routing variable byte-length instructions Dec 20, 1999 Issued
Array ( [id] => 1024936 [patent_doc_number] => 06889319 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-05-03 [patent_title] => 'Method and apparatus for entering and exiting multiple threads within a multithreaded processor' [patent_app_type] => utility [patent_app_number] => 09/458570 [patent_app_country] => US [patent_app_date] => 1999-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 24 [patent_no_of_words] => 16371 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/889/06889319.pdf [firstpage_image] =>[orig_patent_app_number] => 09458570 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/458570
Method and apparatus for entering and exiting multiple threads within a multithreaded processor Dec 8, 1999 Issued
Array ( [id] => 1213956 [patent_doc_number] => 06714904 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-03-30 [patent_title] => 'System for using rate of exception event generation during execution of translated instructions to control optimization of the translated instructions' [patent_app_type] => B1 [patent_app_number] => 09/417358 [patent_app_country] => US [patent_app_date] => 1999-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 5952 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/714/06714904.pdf [firstpage_image] =>[orig_patent_app_number] => 09417358 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/417358
System for using rate of exception event generation during execution of translated instructions to control optimization of the translated instructions Oct 12, 1999 Issued
Array ( [id] => 787815 [patent_doc_number] => 06990658 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-01-24 [patent_title] => 'Method for translating instructions in a speculative microprocessor featuring committing state' [patent_app_type] => utility [patent_app_number] => 09/417980 [patent_app_country] => US [patent_app_date] => 1999-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 3899 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/990/06990658.pdf [firstpage_image] =>[orig_patent_app_number] => 09417980 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/417980
Method for translating instructions in a speculative microprocessor featuring committing state Oct 12, 1999 Issued
Array ( [id] => 787815 [patent_doc_number] => 06990658 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-01-24 [patent_title] => 'Method for translating instructions in a speculative microprocessor featuring committing state' [patent_app_type] => utility [patent_app_number] => 09/417980 [patent_app_country] => US [patent_app_date] => 1999-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 3899 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/990/06990658.pdf [firstpage_image] =>[orig_patent_app_number] => 09417980 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/417980
Method for translating instructions in a speculative microprocessor featuring committing state Oct 12, 1999 Issued
Array ( [id] => 1033954 [patent_doc_number] => 06880152 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-04-12 [patent_title] => 'Method of determining a mode of code generation' [patent_app_type] => utility [patent_app_number] => 09/417979 [patent_app_country] => US [patent_app_date] => 1999-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3896 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/880/06880152.pdf [firstpage_image] =>[orig_patent_app_number] => 09417979 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/417979
Method of determining a mode of code generation Oct 12, 1999 Issued
Array ( [id] => 69252 [patent_doc_number] => 07761857 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-07-20 [patent_title] => 'Method for switching between interpretation and dynamic translation in a processor system based upon code sequence execution counts' [patent_app_type] => utility [patent_app_number] => 09/417332 [patent_app_country] => US [patent_app_date] => 1999-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3907 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/761/07761857.pdf [firstpage_image] =>[orig_patent_app_number] => 09417332 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/417332
Method for switching between interpretation and dynamic translation in a processor system based upon code sequence execution counts Oct 12, 1999 Issued
Array ( [id] => 787815 [patent_doc_number] => 06990658 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-01-24 [patent_title] => 'Method for translating instructions in a speculative microprocessor featuring committing state' [patent_app_type] => utility [patent_app_number] => 09/417980 [patent_app_country] => US [patent_app_date] => 1999-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 3899 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/990/06990658.pdf [firstpage_image] =>[orig_patent_app_number] => 09417980 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/417980
Method for translating instructions in a speculative microprocessor featuring committing state Oct 12, 1999 Issued
Array ( [id] => 787815 [patent_doc_number] => 06990658 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-01-24 [patent_title] => 'Method for translating instructions in a speculative microprocessor featuring committing state' [patent_app_type] => utility [patent_app_number] => 09/417980 [patent_app_country] => US [patent_app_date] => 1999-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 3899 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/990/06990658.pdf [firstpage_image] =>[orig_patent_app_number] => 09417980 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/417980
Method for translating instructions in a speculative microprocessor featuring committing state Oct 12, 1999 Issued
Array ( [id] => 1297187 [patent_doc_number] => 06633971 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-10-14 [patent_title] => 'Mechanism for forward data in a processor pipeline using a single pipefile connected to the pipeline' [patent_app_type] => B2 [patent_app_number] => 09/411431 [patent_app_country] => US [patent_app_date] => 1999-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 6618 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/633/06633971.pdf [firstpage_image] =>[orig_patent_app_number] => 09411431 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/411431
Mechanism for forward data in a processor pipeline using a single pipefile connected to the pipeline Sep 30, 1999 Issued
Array ( [id] => 4312468 [patent_doc_number] => 06237084 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-22 [patent_title] => 'Processor which can favorably execute a rounding process composed of positive conversion and saturated calculation processing' [patent_app_type] => 1 [patent_app_number] => 9/399577 [patent_app_country] => US [patent_app_date] => 1999-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 18 [patent_no_of_words] => 13995 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/237/06237084.pdf [firstpage_image] =>[orig_patent_app_number] => 399577 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/399577
Processor which can favorably execute a rounding process composed of positive conversion and saturated calculation processing Sep 19, 1999 Issued
Array ( [id] => 1580405 [patent_doc_number] => 06470445 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-22 [patent_title] => 'Preventing write-after-write data hazards by canceling earlier write when no intervening instruction uses value to be written by the earlier write' [patent_app_type] => B1 [patent_app_number] => 09/391023 [patent_app_country] => US [patent_app_date] => 1999-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 7312 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/470/06470445.pdf [firstpage_image] =>[orig_patent_app_number] => 09391023 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/391023
Preventing write-after-write data hazards by canceling earlier write when no intervening instruction uses value to be written by the earlier write Sep 6, 1999 Issued
Array ( [id] => 860403 [patent_doc_number] => 07376814 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-05-20 [patent_title] => 'Method for forming variable length instructions in a processing system' [patent_app_type] => utility [patent_app_number] => 09/391647 [patent_app_country] => US [patent_app_date] => 1999-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 17 [patent_no_of_words] => 3272 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/376/07376814.pdf [firstpage_image] =>[orig_patent_app_number] => 09391647 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/391647
Method for forming variable length instructions in a processing system Sep 6, 1999 Issued
Array ( [id] => 1319147 [patent_doc_number] => 06618802 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-09-09 [patent_title] => 'Superscalar processing system and method for selectively stalling instructions within an issue group' [patent_app_type] => B1 [patent_app_number] => 09/390199 [patent_app_country] => US [patent_app_date] => 1999-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 7201 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/618/06618802.pdf [firstpage_image] =>[orig_patent_app_number] => 09390199 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/390199
Superscalar processing system and method for selectively stalling instructions within an issue group Sep 6, 1999 Issued
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