Alexander Marion Weddle

Array ( [id] => 6741652 [patent_doc_number] => 20030159021 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-08-21 [patent_title] => 'SELECTED REGISTER DECODE VALUES FOR PIPELINE STAGE REGISTER ADDRESSING' [patent_app_type] => new [patent_app_number] => 09/390079 [patent_app_country] => US [patent_app_date] => 1999-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5568 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0159/20030159021.pdf [firstpage_image] =>[orig_patent_app_number] => 09390079 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7644124 [patent_doc_number] => 06473850 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-29 [patent_title] => 'System and method for handling instructions occurring after an ISYNC instruction' [patent_app_type] => B1 [patent_app_number] => 09/389197 [patent_app_country] => US [patent_app_date] => 1999-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3609 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 4 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/473/06473850.pdf [firstpage_image] =>[orig_patent_app_number] => 09389197 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1587485 [patent_doc_number] => 06425072 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-23 [patent_title] => 'System for implementing a register free-list by using swap bit to select first or second register tag in retire queue' [patent_app_type] => B1 [patent_app_number] => 09/387026 [patent_app_country] => US [patent_app_date] => 1999-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 18 [patent_no_of_words] => 15116 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/425/06425072.pdf [firstpage_image] =>[orig_patent_app_number] => 09387026 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1329245 [patent_doc_number] => 06606704 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-08-12 [patent_title] => 'Parallel multithreaded processor with plural microengines executing multiple threads each microengine having loadable microcode' [patent_app_type] => B1 [patent_app_number] => 09/387111 [patent_app_country] => US [patent_app_date] => 1999-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 11007 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/606/06606704.pdf [firstpage_image] =>[orig_patent_app_number] => 09387111 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7982593 [patent_doc_number] => 08074055 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-12-06 [patent_title] => 'Altering data storage conventions of a processor when execution flows from first architecture code to second architecture code' [patent_app_type] => utility [patent_app_number] => 09/385394 [patent_app_country] => US [patent_app_date] => 1999-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 41 [patent_figures_cnt] => 50 [patent_no_of_words] => 62296 [patent_no_of_claims] => 47 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/074/08074055.pdf [firstpage_image] =>[orig_patent_app_number] => 09385394 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1109814 [patent_doc_number] => 06813701 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-11-02 [patent_title] => 'Method and apparatus for transferring vector data between memory and a register file' [patent_app_type] => B1 [patent_app_number] => 09/375328 [patent_app_country] => US [patent_app_date] => 1999-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 9017 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/813/06813701.pdf [firstpage_image] =>[orig_patent_app_number] => 09375328 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1429045 [patent_doc_number] => 06513107 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-01-28 [patent_title] => 'Vector transfer system generating address error exception when vector to be transferred does not start and end on same memory page' [patent_app_type] => B1 [patent_app_number] => 09/375873 [patent_app_country] => US [patent_app_date] => 1999-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 9117 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/513/06513107.pdf [firstpage_image] =>[orig_patent_app_number] => 09375873 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1311443 [patent_doc_number] => 06625720 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-09-23 [patent_title] => 'System for posting vector synchronization instructions to vector instruction queue to separate vector instructions from different application programs' [patent_app_type] => B1 [patent_app_number] => 09/375718 [patent_app_country] => US [patent_app_date] => 1999-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 8943 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/625/06625720.pdf [firstpage_image] =>[orig_patent_app_number] => 09375718 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4373575 [patent_doc_number] => 06202120 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-13 [patent_title] => 'System and method for accessing data between a host bus and a system memory bus where the system memory bus has a data path that is twice the width of the data path for the host bus' [patent_app_type] => 1 [patent_app_number] => 9/364480 [patent_app_country] => US [patent_app_date] => 1999-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6460 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/202/06202120.pdf [firstpage_image] =>[orig_patent_app_number] => 364480 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4391964 [patent_doc_number] => 06289440 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-11 [patent_title] => 'Virtual computer of plural FPG\'s successively reconfigured in response to a succession of inputs' [patent_app_type] => 1 [patent_app_number] => 9/353522 [patent_app_country] => US [patent_app_date] => 1999-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 25 [patent_no_of_words] => 11191 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/289/06289440.pdf [firstpage_image] =>[orig_patent_app_number] => 353522 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4324021 [patent_doc_number] => 06327607 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-12-04 [patent_title] => 'Invocation architecture for generally concurrent process resolution' [patent_app_type] => 1 [patent_app_number] => 9/339909 [patent_app_country] => US [patent_app_date] => 1999-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 34 [patent_no_of_words] => 10808 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/327/06327607.pdf [firstpage_image] =>[orig_patent_app_number] => 339909 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1201041 [patent_doc_number] => 06728871 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-04-27 [patent_title] => 'Runtime configurable arithmetic and logic cell' [patent_app_type] => B1 [patent_app_number] => 09/329132 [patent_app_country] => US [patent_app_date] => 1999-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 29 [patent_no_of_words] => 9894 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/728/06728871.pdf [firstpage_image] =>[orig_patent_app_number] => 09329132 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4151946 [patent_doc_number] => 06035387 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-07 [patent_title] => 'System for packing variable length instructions into fixed length blocks with indications of instruction beginning, ending, and offset within block' [patent_app_type] => 1 [patent_app_number] => 9/324236 [patent_app_country] => US [patent_app_date] => 1999-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 15 [patent_no_of_words] => 19078 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 251 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/035/06035387.pdf [firstpage_image] =>[orig_patent_app_number] => 324236 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1508436 [patent_doc_number] => 06466836 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-15 [patent_title] => 'Method and apparatus for encoding or decoding a human readable representation of options differentiating products or services' [patent_app_type] => B1 [patent_app_number] => 09/301046 [patent_app_country] => US [patent_app_date] => 1999-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 4792 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 14 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/466/06466836.pdf [firstpage_image] =>[orig_patent_app_number] => 09301046 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1513340 [patent_doc_number] => 06442680 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-27 [patent_title] => 'Method and system for compressing reduced instruction set computer (RISC) executable code' [patent_app_type] => B1 [patent_app_number] => 09/239259 [patent_app_country] => US [patent_app_date] => 1999-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2503 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/442/06442680.pdf [firstpage_image] =>[orig_patent_app_number] => 09239259 [rel_patent_id] =>[rel_patent_doc_number] =>)