Search

Alexander O. Boakye

Examiner (ID: 8184, Phone: (571)272-3183 , Office: P/2471 )

Most Active Art Unit
2471
Art Unit(s)
2739, 2666, 2663, 2733, 2667, 2616, 2471, 2416
Total Applications
1077
Issued Applications
944
Pending Applications
70
Abandoned Applications
63

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3593889 [patent_doc_number] => 05517131 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-05-14 [patent_title] => 'TTL input buffer with on-chip reference bias regulator and decoupling capacitor' [patent_app_type] => 1 [patent_app_number] => 8/295322 [patent_app_country] => US [patent_app_date] => 1994-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2942 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/517/05517131.pdf [firstpage_image] =>[orig_patent_app_number] => 295322 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/295322
TTL input buffer with on-chip reference bias regulator and decoupling capacitor Aug 22, 1994 Issued
Array ( [id] => 3530634 [patent_doc_number] => 05504441 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-04-02 [patent_title] => 'Two-phase overlapping clocking technique for digital dynamic circuits' [patent_app_type] => 1 [patent_app_number] => 8/293232 [patent_app_country] => US [patent_app_date] => 1994-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 18 [patent_no_of_words] => 2904 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/504/05504441.pdf [firstpage_image] =>[orig_patent_app_number] => 293232 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/293232
Two-phase overlapping clocking technique for digital dynamic circuits Aug 18, 1994 Issued
Array ( [id] => 3429039 [patent_doc_number] => 05422581 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-06-06 [patent_title] => 'Gate array cell with predefined connection patterns' [patent_app_type] => 1 [patent_app_number] => 8/291639 [patent_app_country] => US [patent_app_date] => 1994-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1779 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/422/05422581.pdf [firstpage_image] =>[orig_patent_app_number] => 291639 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/291639
Gate array cell with predefined connection patterns Aug 16, 1994 Issued
Array ( [id] => 3467089 [patent_doc_number] => 05469081 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-11-21 [patent_title] => 'Circuit for interconnecting integrated semiconductor circuits' [patent_app_type] => 1 [patent_app_number] => 8/292142 [patent_app_country] => US [patent_app_date] => 1994-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 37 [patent_no_of_words] => 8764 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 249 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/469/05469081.pdf [firstpage_image] =>[orig_patent_app_number] => 292142 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/292142
Circuit for interconnecting integrated semiconductor circuits Aug 7, 1994 Issued
Array ( [id] => 3502357 [patent_doc_number] => 05532616 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-07-02 [patent_title] => 'On-chip series terminated CMOS(Bi-CMOS) driver' [patent_app_type] => 1 [patent_app_number] => 8/283436 [patent_app_country] => US [patent_app_date] => 1994-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 12 [patent_no_of_words] => 6907 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/532/05532616.pdf [firstpage_image] =>[orig_patent_app_number] => 283436 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/283436
On-chip series terminated CMOS(Bi-CMOS) driver Jul 31, 1994 Issued
Array ( [id] => 3434344 [patent_doc_number] => 05463332 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-10-31 [patent_title] => 'Multiple differential input ECL or/nor gate' [patent_app_type] => 1 [patent_app_number] => 8/279035 [patent_app_country] => US [patent_app_date] => 1994-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 4219 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/463/05463332.pdf [firstpage_image] =>[orig_patent_app_number] => 279035 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/279035
Multiple differential input ECL or/nor gate Jul 21, 1994 Issued
Array ( [id] => 3467130 [patent_doc_number] => 05469084 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-11-21 [patent_title] => 'BiCMOS output driver' [patent_app_type] => 1 [patent_app_number] => 8/279495 [patent_app_country] => US [patent_app_date] => 1994-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 4306 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 28 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/469/05469084.pdf [firstpage_image] =>[orig_patent_app_number] => 279495 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/279495
BiCMOS output driver Jul 21, 1994 Issued
Array ( [id] => 3512436 [patent_doc_number] => 05570037 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-10-29 [patent_title] => 'Switchable differential terminator' [patent_app_type] => 1 [patent_app_number] => 8/278025 [patent_app_country] => US [patent_app_date] => 1994-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3174 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 36 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/570/05570037.pdf [firstpage_image] =>[orig_patent_app_number] => 278025 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/278025
Switchable differential terminator Jul 19, 1994 Issued
Array ( [id] => 3424475 [patent_doc_number] => 05479111 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-12-26 [patent_title] => 'Signal transmitting device in a semiconductor apparatus' [patent_app_type] => 1 [patent_app_number] => 8/273125 [patent_app_country] => US [patent_app_date] => 1994-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5114 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 35 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/479/05479111.pdf [firstpage_image] =>[orig_patent_app_number] => 273125 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/273125
Signal transmitting device in a semiconductor apparatus Jul 13, 1994 Issued
Array ( [id] => 3434312 [patent_doc_number] => 05463330 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-10-31 [patent_title] => 'CMOS input circuit' [patent_app_type] => 1 [patent_app_number] => 8/273935 [patent_app_country] => US [patent_app_date] => 1994-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 9476 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 294 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/463/05463330.pdf [firstpage_image] =>[orig_patent_app_number] => 273935 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/273935
CMOS input circuit Jul 11, 1994 Issued
Array ( [id] => 3510603 [patent_doc_number] => 05514981 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-05-07 [patent_title] => 'Reset dominant level-shift circuit for noise immunity' [patent_app_type] => 1 [patent_app_number] => 8/273695 [patent_app_country] => US [patent_app_date] => 1994-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 8 [patent_no_of_words] => 2442 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/514/05514981.pdf [firstpage_image] =>[orig_patent_app_number] => 273695 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/273695
Reset dominant level-shift circuit for noise immunity Jul 11, 1994 Issued
Array ( [id] => 3462906 [patent_doc_number] => 05473272 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-12-05 [patent_title] => 'Digital differential amplifier switching stage with current switch' [patent_app_type] => 1 [patent_app_number] => 8/267822 [patent_app_country] => US [patent_app_date] => 1994-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2287 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 333 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/473/05473272.pdf [firstpage_image] =>[orig_patent_app_number] => 267822 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/267822
Digital differential amplifier switching stage with current switch Jun 27, 1994 Issued
Array ( [id] => 3522863 [patent_doc_number] => 05506521 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-04-09 [patent_title] => 'ECL driver with adjustable rise and fall times, and method therefor' [patent_app_type] => 1 [patent_app_number] => 8/259601 [patent_app_country] => US [patent_app_date] => 1994-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 27 [patent_no_of_words] => 10075 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 322 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/506/05506521.pdf [firstpage_image] =>[orig_patent_app_number] => 259601 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/259601
ECL driver with adjustable rise and fall times, and method therefor Jun 12, 1994 Issued
Array ( [id] => 3424544 [patent_doc_number] => 05479116 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-12-26 [patent_title] => 'Level conversion circuits for converting a digital input signal varying between first and second voltage levels to a digital output signal varying between first and third voltage levels' [patent_app_type] => 1 [patent_app_number] => 8/258525 [patent_app_country] => US [patent_app_date] => 1994-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 3890 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 236 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/479/05479116.pdf [firstpage_image] =>[orig_patent_app_number] => 258525 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/258525
Level conversion circuits for converting a digital input signal varying between first and second voltage levels to a digital output signal varying between first and third voltage levels Jun 9, 1994 Issued
Array ( [id] => 3594463 [patent_doc_number] => 05497109 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-03-05 [patent_title] => 'Integrated circuit with reduced clock skew' [patent_app_type] => 1 [patent_app_number] => 8/252520 [patent_app_country] => US [patent_app_date] => 1994-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 12158 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/497/05497109.pdf [firstpage_image] =>[orig_patent_app_number] => 252520 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/252520
Integrated circuit with reduced clock skew May 31, 1994 Issued
Array ( [id] => 3447155 [patent_doc_number] => 05430390 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-07-04 [patent_title] => 'Programmable application specific integrated circuit and logic cell therefor' [patent_app_type] => 1 [patent_app_number] => 8/245309 [patent_app_country] => US [patent_app_date] => 1994-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 6932 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/430/05430390.pdf [firstpage_image] =>[orig_patent_app_number] => 245309 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/245309
Programmable application specific integrated circuit and logic cell therefor May 16, 1994 Issued
Array ( [id] => 3117170 [patent_doc_number] => 05465057 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-11-07 [patent_title] => 'Level conversion circuit for signal of ECL-level' [patent_app_type] => 1 [patent_app_number] => 8/231059 [patent_app_country] => US [patent_app_date] => 1994-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 2764 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 218 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/465/05465057.pdf [firstpage_image] =>[orig_patent_app_number] => 231059 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/231059
Level conversion circuit for signal of ECL-level Apr 21, 1994 Issued
Array ( [id] => 3569536 [patent_doc_number] => 05483179 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-01-09 [patent_title] => 'Data output drivers with pull-up devices' [patent_app_type] => 1 [patent_app_number] => 8/230265 [patent_app_country] => US [patent_app_date] => 1994-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 3086 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/483/05483179.pdf [firstpage_image] =>[orig_patent_app_number] => 230265 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/230265
Data output drivers with pull-up devices Apr 19, 1994 Issued
Array ( [id] => 3617764 [patent_doc_number] => 05534790 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-07-09 [patent_title] => 'Current transition rate control circuit' [patent_app_type] => 1 [patent_app_number] => 8/227162 [patent_app_country] => US [patent_app_date] => 1994-04-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3902 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 24 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/534/05534790.pdf [firstpage_image] =>[orig_patent_app_number] => 227162 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/227162
Current transition rate control circuit Apr 12, 1994 Issued
Array ( [id] => 3117114 [patent_doc_number] => 05465054 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-11-07 [patent_title] => 'High voltage CMOS logic using low voltage CMOS process' [patent_app_type] => 1 [patent_app_number] => 8/224762 [patent_app_country] => US [patent_app_date] => 1994-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 15 [patent_no_of_words] => 8908 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 234 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/465/05465054.pdf [firstpage_image] =>[orig_patent_app_number] => 224762 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/224762
High voltage CMOS logic using low voltage CMOS process Apr 7, 1994 Issued
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