Search

Alexander O Williams

Examiner (ID: 12148, Phone: (571)272-1924 , Office: P/2826 )

Most Active Art Unit
2826
Art Unit(s)
2826, 2811, 2508
Total Applications
2764
Issued Applications
2318
Pending Applications
64
Abandoned Applications
383

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16944209 [patent_doc_number] => 11056460 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-07-06 [patent_title] => Method for producing an electric circuit comprising a circuit carrier, contact areas, and an insulating body [patent_app_type] => utility [patent_app_number] => 16/481758 [patent_app_country] => US [patent_app_date] => 2018-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 13 [patent_no_of_words] => 8469 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16481758 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/481758
Method for producing an electric circuit comprising a circuit carrier, contact areas, and an insulating body Jan 21, 2018 Issued
Array ( [id] => 12740983 [patent_doc_number] => 20180138828 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-17 [patent_title] => SEMICONDUCTOR MODULE [patent_app_type] => utility [patent_app_number] => 15/867978 [patent_app_country] => US [patent_app_date] => 2018-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19597 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 297 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15867978 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/867978
SEMICONDUCTOR MODULE Jan 10, 2018 Abandoned
Array ( [id] => 15428035 [patent_doc_number] => 10546957 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-01-28 [patent_title] => Nanosheet FET including all-around source/drain contact [patent_app_type] => utility [patent_app_number] => 15/868742 [patent_app_country] => US [patent_app_date] => 2018-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 38 [patent_no_of_words] => 6905 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 40 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15868742 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/868742
Nanosheet FET including all-around source/drain contact Jan 10, 2018 Issued
Array ( [id] => 14889021 [patent_doc_number] => 10424561 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-09-24 [patent_title] => Integrated circuit structures with recessed conductive contacts for package on package [patent_app_type] => utility [patent_app_number] => 15/863821 [patent_app_country] => US [patent_app_date] => 2018-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 19 [patent_no_of_words] => 8921 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 216 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15863821 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/863821
Integrated circuit structures with recessed conductive contacts for package on package Jan 4, 2018 Issued
Array ( [id] => 14300891 [patent_doc_number] => 10290576 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-05-14 [patent_title] => Stress reduction apparatus with an inverted cup-shaped layer [patent_app_type] => utility [patent_app_number] => 15/860829 [patent_app_country] => US [patent_app_date] => 2018-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2905 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15860829 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/860829
Stress reduction apparatus with an inverted cup-shaped layer Jan 2, 2018 Issued
Array ( [id] => 13306555 [patent_doc_number] => 20180204814 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-07-19 [patent_title] => METHOD FOR PREPARING A SEMICONDUCTOR PACKAGE [patent_app_type] => utility [patent_app_number] => 15/853477 [patent_app_country] => US [patent_app_date] => 2017-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5563 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15853477 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/853477
METHOD FOR PREPARING A SEMICONDUCTOR PACKAGE Dec 21, 2017 Abandoned
Array ( [id] => 12823738 [patent_doc_number] => 20180166418 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-06-14 [patent_title] => METHOD FOR PREPARING A WAFER LEVEL CHIP-ON-CHIP SEMICONDUCTOR STRUCTURE [patent_app_type] => utility [patent_app_number] => 15/853522 [patent_app_country] => US [patent_app_date] => 2017-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4557 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15853522 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/853522
METHOD FOR PREPARING A WAFER LEVEL CHIP-ON-CHIP SEMICONDUCTOR STRUCTURE Dec 21, 2017 Abandoned
Array ( [id] => 13740633 [patent_doc_number] => 20180374786 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-12-27 [patent_title] => FEEDTHROUGH ASSEMBLIES AND METHODS OF FORMING SAME [patent_app_type] => utility [patent_app_number] => 15/850061 [patent_app_country] => US [patent_app_date] => 2017-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15016 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15850061 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/850061
Feedthrough assemblies and methods of forming same Dec 20, 2017 Issued
Array ( [id] => 14191325 [patent_doc_number] => 20190115368 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-04-18 [patent_title] => ARRAY SUBSTRATE AND DISPLAY PANEL USING THE SAME [patent_app_type] => utility [patent_app_number] => 15/745548 [patent_app_country] => US [patent_app_date] => 2017-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5828 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 274 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15745548 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/745548
Array substrate and display panel using the same Dec 18, 2017 Issued
Array ( [id] => 14526233 [patent_doc_number] => 10340387 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-07-02 [patent_title] => Low temperature poly-silicon thin film transistor, manufacturing method thereof, and array substrate [patent_app_type] => utility [patent_app_number] => 15/745073 [patent_app_country] => US [patent_app_date] => 2017-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 3624 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 212 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15745073 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/745073
Low temperature poly-silicon thin film transistor, manufacturing method thereof, and array substrate Dec 17, 2017 Issued
Array ( [id] => 17092897 [patent_doc_number] => 11121095 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-09-14 [patent_title] => Semiconductor device having electromagnetic wave absorbing layer with heat dissipating vias [patent_app_type] => utility [patent_app_number] => 16/463660 [patent_app_country] => US [patent_app_date] => 2017-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 41 [patent_no_of_words] => 8752 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16463660 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/463660
Semiconductor device having electromagnetic wave absorbing layer with heat dissipating vias Dec 14, 2017 Issued
Array ( [id] => 16356571 [patent_doc_number] => 10797089 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-10-06 [patent_title] => Display device having compensating capacitor and method of manufacturing the same [patent_app_type] => utility [patent_app_number] => 16/313619 [patent_app_country] => US [patent_app_date] => 2017-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 3486 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16313619 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/313619
Display device having compensating capacitor and method of manufacturing the same Dec 11, 2017 Issued
Array ( [id] => 14366775 [patent_doc_number] => 10304699 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-05-28 [patent_title] => Adhesive-bonded thermal interface structures [patent_app_type] => utility [patent_app_number] => 15/838629 [patent_app_country] => US [patent_app_date] => 2017-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 14630 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 288 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15838629 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/838629
Adhesive-bonded thermal interface structures Dec 11, 2017 Issued
Array ( [id] => 15388801 [patent_doc_number] => 10535599 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-01-14 [patent_title] => Vertical memory device including common source line structure [patent_app_type] => utility [patent_app_number] => 15/831498 [patent_app_country] => US [patent_app_date] => 2017-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 32 [patent_no_of_words] => 18481 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 313 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15831498 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/831498
Vertical memory device including common source line structure Dec 4, 2017 Issued
Array ( [id] => 14351223 [patent_doc_number] => 20190157584 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-23 [patent_title] => FLEXIBLE ARRAY SUBSTRATE AND METHOD FOR MANUFACTURING SAME [patent_app_type] => utility [patent_app_number] => 15/743281 [patent_app_country] => US [patent_app_date] => 2017-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3350 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15743281 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/743281
Flexible array substrate and method for manufacturing same Nov 29, 2017 Issued
Array ( [id] => 14671965 [patent_doc_number] => 10373902 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-08-06 [patent_title] => Fully molded miniaturized semiconductor module [patent_app_type] => utility [patent_app_number] => 15/825055 [patent_app_country] => US [patent_app_date] => 2017-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 16 [patent_no_of_words] => 13039 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15825055 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/825055
Fully molded miniaturized semiconductor module Nov 27, 2017 Issued
Array ( [id] => 15274997 [patent_doc_number] => 20190386233 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-12-19 [patent_title] => FABRICATING METHOD OF QLED DEVICE AND QLED DEVICE [patent_app_type] => utility [patent_app_number] => 15/745036 [patent_app_country] => US [patent_app_date] => 2017-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4874 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15745036 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/745036
Fabricating method of QLED device and QLED device Nov 26, 2017 Issued
Array ( [id] => 14769303 [patent_doc_number] => 10396053 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-08-27 [patent_title] => Semiconductor logic device and system and method of embedded packaging of same [patent_app_type] => utility [patent_app_number] => 15/816396 [patent_app_country] => US [patent_app_date] => 2017-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 24 [patent_no_of_words] => 9771 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15816396 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/816396
Semiconductor logic device and system and method of embedded packaging of same Nov 16, 2017 Issued
Array ( [id] => 14350509 [patent_doc_number] => 20190157227 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-23 [patent_title] => SEMICONDUCTOR LOGIC DEVICE AND SYSTEM AND METHOD OF EMBEDDED PACKAGING OF SAME [patent_app_type] => utility [patent_app_number] => 15/816360 [patent_app_country] => US [patent_app_date] => 2017-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9262 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -25 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15816360 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/816360
Semiconductor logic device and system and method of embedded packaging of same Nov 16, 2017 Issued
Array ( [id] => 15315523 [patent_doc_number] => 10522477 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-12-31 [patent_title] => Method of making package assembly including stress relief structures [patent_app_type] => utility [patent_app_number] => 15/810602 [patent_app_country] => US [patent_app_date] => 2017-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 16 [patent_no_of_words] => 3572 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15810602 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/810602
Method of making package assembly including stress relief structures Nov 12, 2017 Issued
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