Search

Alexander O Williams

Examiner (ID: 12148, Phone: (571)272-1924 , Office: P/2826 )

Most Active Art Unit
2826
Art Unit(s)
2826, 2811, 2508
Total Applications
2764
Issued Applications
2318
Pending Applications
64
Abandoned Applications
383

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 12019717 [patent_doc_number] => 09812427 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-11-07 [patent_title] => 'Package on-package (PoP) structure including stud bulbs' [patent_app_type] => utility [patent_app_number] => 15/288751 [patent_app_country] => US [patent_app_date] => 2016-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 40 [patent_no_of_words] => 6409 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15288751 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/288751
Package on-package (PoP) structure including stud bulbs Oct 6, 2016 Issued
Array ( [id] => 11397983 [patent_doc_number] => 20170018520 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-01-19 [patent_title] => 'USING AN INTERCONNECT BUMP TO TRAVERSE THROUGH A PASSIVATION LAYER OF A SEMICONDUCTOR DIE' [patent_app_type] => utility [patent_app_number] => 15/278960 [patent_app_country] => US [patent_app_date] => 2016-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 5394 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15278960 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/278960
USING AN INTERCONNECT BUMP TO TRAVERSE THROUGH A PASSIVATION LAYER OF A SEMICONDUCTOR DIE Sep 27, 2016 Abandoned
Array ( [id] => 11385934 [patent_doc_number] => 20170011990 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-01-12 [patent_title] => 'SEMICONDUCTOR DEVICE WITH LEAD TERMINALS HAVING PORTIONS THEREOF EXTENDING OBLIQUELY' [patent_app_type] => utility [patent_app_number] => 15/272557 [patent_app_country] => US [patent_app_date] => 2016-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5037 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15272557 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/272557
Semiconductor device with lead terminals having portions thereof extending obliquely Sep 21, 2016 Issued
Array ( [id] => 13099067 [patent_doc_number] => 10068879 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-09-04 [patent_title] => Three-dimensional stacked integrated circuit devices and methods of assembling the same [patent_app_type] => utility [patent_app_number] => 15/269576 [patent_app_country] => US [patent_app_date] => 2016-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6286 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15269576 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/269576
Three-dimensional stacked integrated circuit devices and methods of assembling the same Sep 18, 2016 Issued
Array ( [id] => 12263791 [patent_doc_number] => 20180082987 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-03-22 [patent_title] => 'PACKAGE STRUCTURE WITH DUMMY DIE' [patent_app_type] => utility [patent_app_number] => 15/268843 [patent_app_country] => US [patent_app_date] => 2016-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 6864 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15268843 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/268843
Package structure with dummy die Sep 18, 2016 Issued
Array ( [id] => 12102109 [patent_doc_number] => 09859208 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-01-02 [patent_title] => 'Bottom self-aligned via' [patent_app_type] => utility [patent_app_number] => 15/268604 [patent_app_country] => US [patent_app_date] => 2016-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 15 [patent_no_of_words] => 2726 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15268604 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/268604
Bottom self-aligned via Sep 17, 2016 Issued
Array ( [id] => 12250140 [patent_doc_number] => 09922922 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-03-20 [patent_title] => 'Microchip with cap layer for redistribution circuitry and method of manufacturing the same' [patent_app_type] => utility [patent_app_number] => 15/268169 [patent_app_country] => US [patent_app_date] => 2016-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 17 [patent_no_of_words] => 5403 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15268169 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/268169
Microchip with cap layer for redistribution circuitry and method of manufacturing the same Sep 15, 2016 Issued
Array ( [id] => 14333069 [patent_doc_number] => 10297563 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-05-21 [patent_title] => Copper seed layer and nickel-tin microbump structures [patent_app_type] => utility [patent_app_number] => 15/267065 [patent_app_country] => US [patent_app_date] => 2016-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6181 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15267065 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/267065
Copper seed layer and nickel-tin microbump structures Sep 14, 2016 Issued
Array ( [id] => 12953590 [patent_doc_number] => 09837341 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-12-05 [patent_title] => Tin-zinc microbump structures [patent_app_type] => utility [patent_app_number] => 15/267040 [patent_app_country] => US [patent_app_date] => 2016-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5961 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15267040 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/267040
Tin-zinc microbump structures Sep 14, 2016 Issued
Array ( [id] => 11339567 [patent_doc_number] => 20160365323 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-12-15 [patent_title] => 'ELECTRONIC DEVICES WITH ATTACHED DIE STRUCTURES AND METHODS OF FORMATION OF SUCH DEVICES' [patent_app_type] => utility [patent_app_number] => 15/247393 [patent_app_country] => US [patent_app_date] => 2016-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 10450 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15247393 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/247393
Electronic devices with semiconductor die attached with sintered metallic layers, and methods of formation of such devices Aug 24, 2016 Issued
Array ( [id] => 11571796 [patent_doc_number] => 20170110440 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-04-20 [patent_title] => 'SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING SAME' [patent_app_type] => utility [patent_app_number] => 15/245306 [patent_app_country] => US [patent_app_date] => 2016-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 6416 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15245306 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/245306
SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING SAME Aug 23, 2016 Abandoned
Array ( [id] => 11475530 [patent_doc_number] => 20170062313 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-02 [patent_title] => 'SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 15/245298 [patent_app_country] => US [patent_app_date] => 2016-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 6365 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15245298 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/245298
Semiconductor device having wire bonding connection and method for manufacturing the same Aug 23, 2016 Issued
Array ( [id] => 11840094 [patent_doc_number] => 20170221813 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-08-03 [patent_title] => 'INTEGRATED CIRCUIT DEVICE INCLUDING VERTICAL MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 15/245441 [patent_app_country] => US [patent_app_date] => 2016-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 33 [patent_figures_cnt] => 33 [patent_no_of_words] => 18966 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15245441 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/245441
Integrated circuit device including vertical memory device and method of manufacturing the same Aug 23, 2016 Issued
Array ( [id] => 12223400 [patent_doc_number] => 20180061760 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-03-01 [patent_title] => 'SUBSTRATE CONTACT USING DUAL SIDED SILICIDATION' [patent_app_type] => utility [patent_app_number] => 15/245087 [patent_app_country] => US [patent_app_date] => 2016-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 8373 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15245087 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/245087
Substrate contact using dual sided silicidation Aug 22, 2016 Issued
Array ( [id] => 11694410 [patent_doc_number] => 20170170127 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-15 [patent_title] => 'SEMICONDUCTORS, PACKAGES, WAFER LEVEL PACKAGES, AND METHODS OF MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 15/243296 [patent_app_country] => US [patent_app_date] => 2016-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 33 [patent_figures_cnt] => 33 [patent_no_of_words] => 11744 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15243296 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/243296
Wafer level packages and electronics system including the same Aug 21, 2016 Issued
Array ( [id] => 12250158 [patent_doc_number] => 09922940 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-03-20 [patent_title] => 'Semiconductor device including air gaps between interconnects and method of manufacturing the same' [patent_app_type] => utility [patent_app_number] => 15/242964 [patent_app_country] => US [patent_app_date] => 2016-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 6139 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15242964 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/242964
Semiconductor device including air gaps between interconnects and method of manufacturing the same Aug 21, 2016 Issued
Array ( [id] => 14769199 [patent_doc_number] => 10396001 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-08-27 [patent_title] => Offset test pads for WLCSP final test [patent_app_type] => utility [patent_app_number] => 15/737470 [patent_app_country] => US [patent_app_date] => 2016-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4142 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15737470 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/737470
Offset test pads for WLCSP final test Aug 14, 2016 Issued
Array ( [id] => 11734661 [patent_doc_number] => 20170196104 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-07-06 [patent_title] => 'LOW COST HERMETIC MICRO-ELECTRONICS' [patent_app_type] => utility [patent_app_number] => 15/212330 [patent_app_country] => US [patent_app_date] => 2016-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4061 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15212330 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/212330
Low cost hermetic micro-electronics Jul 17, 2016 Issued
Array ( [id] => 11425564 [patent_doc_number] => 20170033710 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-02-02 [patent_title] => 'SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 15/194624 [patent_app_country] => US [patent_app_date] => 2016-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 21217 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15194624 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/194624
Semiconductor module Jun 27, 2016 Issued
Array ( [id] => 13785743 [patent_doc_number] => 20190006410 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-01-03 [patent_title] => SOLID-STATE IMAGE SENSING DEVICE, MANUFACTURING METHOD, AND ELECTRONIC APPARATUS [patent_app_type] => utility [patent_app_number] => 15/741365 [patent_app_country] => US [patent_app_date] => 2016-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5251 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15741365 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/741365
Solid-state image sensing device, manufacturing method, and electronic apparatus Jun 23, 2016 Issued
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