Search

Alexander O Williams

Examiner (ID: 12148, Phone: (571)272-1924 , Office: P/2826 )

Most Active Art Unit
2826
Art Unit(s)
2826, 2811, 2508
Total Applications
2764
Issued Applications
2318
Pending Applications
64
Abandoned Applications
383

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 10696910 [patent_doc_number] => 20160043058 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-02-11 [patent_title] => 'SEMICONDUCTOR COOLING STRUCTURE AND METHOD IN A MIXED BONDING PROCESS' [patent_app_type] => utility [patent_app_number] => 14/812702 [patent_app_country] => US [patent_app_date] => 2015-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4606 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14812702 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/812702
Semiconductor cooling method and method of heat dissipation Jul 28, 2015 Issued
Array ( [id] => 10681602 [patent_doc_number] => 20160027747 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-01-28 [patent_title] => 'SEMICONDUCTOR DEVICE WITH FINE PITCH REDISTRIBUTION LAYERS' [patent_app_type] => utility [patent_app_number] => 14/810664 [patent_app_country] => US [patent_app_date] => 2015-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 7627 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14810664 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/810664
Semiconductor device redistribution layer with narrow trace width relative to passivation layer opening Jul 27, 2015 Issued
Array ( [id] => 10725637 [patent_doc_number] => 20160071784 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-03-10 [patent_title] => 'SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME' [patent_app_type] => utility [patent_app_number] => 14/810523 [patent_app_country] => US [patent_app_date] => 2015-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 6251 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14810523 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/810523
Semiconductor package having conductive pillars Jul 27, 2015 Issued
Array ( [id] => 11259371 [patent_doc_number] => 09484275 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-11-01 [patent_title] => 'Semiconductor module for high pressure applications' [patent_app_type] => utility [patent_app_number] => 14/811394 [patent_app_country] => US [patent_app_date] => 2015-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4473 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 200 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14811394 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/811394
Semiconductor module for high pressure applications Jul 27, 2015 Issued
Array ( [id] => 11681339 [patent_doc_number] => 09679873 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-06-13 [patent_title] => 'Low profile integrated circuit (IC) package comprising a plurality of dies' [patent_app_type] => utility [patent_app_number] => 14/811261 [patent_app_country] => US [patent_app_date] => 2015-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 24 [patent_no_of_words] => 11976 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14811261 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/811261
Low profile integrated circuit (IC) package comprising a plurality of dies Jul 27, 2015 Issued
Array ( [id] => 11221592 [patent_doc_number] => 09449935 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-09-20 [patent_title] => 'Wafer level package and fabrication method thereof' [patent_app_type] => utility [patent_app_number] => 14/810415 [patent_app_country] => US [patent_app_date] => 2015-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 2050 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14810415 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/810415
Wafer level package and fabrication method thereof Jul 26, 2015 Issued
Array ( [id] => 11359953 [patent_doc_number] => 09536609 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-01-03 [patent_title] => 'Memory modules with multi-chip packaged integrated circuits having flash memory' [patent_app_type] => utility [patent_app_number] => 14/810346 [patent_app_country] => US [patent_app_date] => 2015-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 17 [patent_no_of_words] => 14530 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14810346 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/810346
Memory modules with multi-chip packaged integrated circuits having flash memory Jul 26, 2015 Issued
Array ( [id] => 11925628 [patent_doc_number] => 09793217 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-10-17 [patent_title] => 'Package-on-package type semiconductor device which is realized through applying not a TSV technology but a fan-out wafer level package technology' [patent_app_type] => utility [patent_app_number] => 14/809710 [patent_app_country] => US [patent_app_date] => 2015-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 8543 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14809710 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/809710
Package-on-package type semiconductor device which is realized through applying not a TSV technology but a fan-out wafer level package technology Jul 26, 2015 Issued
Array ( [id] => 11660161 [patent_doc_number] => 09673173 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-06-06 [patent_title] => 'Integrated circuit package with embedded passive structures' [patent_app_type] => utility [patent_app_number] => 14/808743 [patent_app_country] => US [patent_app_date] => 2015-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4535 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14808743 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/808743
Integrated circuit package with embedded passive structures Jul 23, 2015 Issued
Array ( [id] => 11483390 [patent_doc_number] => 09589945 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-03-07 [patent_title] => 'Semiconductor package having stacked semiconductor chips' [patent_app_type] => utility [patent_app_number] => 14/804880 [patent_app_country] => US [patent_app_date] => 2015-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 19 [patent_no_of_words] => 16623 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14804880 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/804880
Semiconductor package having stacked semiconductor chips Jul 20, 2015 Issued
Array ( [id] => 10440530 [patent_doc_number] => 20150325542 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-11-12 [patent_title] => 'CONDUCTIVE CONTACTS HAVING VARYING WIDTHS AND METHOD OF MANUFACTURING SAME' [patent_app_type] => utility [patent_app_number] => 14/804617 [patent_app_country] => US [patent_app_date] => 2015-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3557 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14804617 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/804617
Conductive contacts having varying widths and method of manufacturing same Jul 20, 2015 Issued
Array ( [id] => 12498402 [patent_doc_number] => 09997428 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-06-12 [patent_title] => Via structures for thermal dissipation [patent_app_type] => utility [patent_app_number] => 14/799534 [patent_app_country] => US [patent_app_date] => 2015-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 13 [patent_no_of_words] => 9123 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14799534 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/799534
Via structures for thermal dissipation Jul 13, 2015 Issued
Array ( [id] => 11050751 [patent_doc_number] => 20160247710 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-08-25 [patent_title] => 'SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 14/796409 [patent_app_country] => US [patent_app_date] => 2015-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4602 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14796409 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/796409
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME Jul 9, 2015 Abandoned
Array ( [id] => 11233773 [patent_doc_number] => 09461007 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-10-04 [patent_title] => 'Wafer-to-wafer bonding structure' [patent_app_type] => utility [patent_app_number] => 14/796506 [patent_app_country] => US [patent_app_date] => 2015-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 26 [patent_no_of_words] => 13711 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14796506 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/796506
Wafer-to-wafer bonding structure Jul 9, 2015 Issued
Array ( [id] => 10666975 [patent_doc_number] => 20160013120 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-01-14 [patent_title] => 'Lead Frame and Semiconductor Device' [patent_app_type] => utility [patent_app_number] => 14/791630 [patent_app_country] => US [patent_app_date] => 2015-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 10576 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14791630 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/791630
Lead frame with anchor-shaped lead Jul 5, 2015 Issued
Array ( [id] => 11760327 [patent_doc_number] => 20170207196 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-07-20 [patent_title] => 'INTEGRATED CIRCUIT STRUCTURES WITH RECESSED CONDUCTIVE CONTACTS FOR PACKAGE ON PACKAGE' [patent_app_type] => utility [patent_app_number] => 15/038008 [patent_app_country] => US [patent_app_date] => 2015-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 9031 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15038008 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/038008
Integrated circuit structures with recessed conductive contacts for package on package Jun 24, 2015 Issued
Array ( [id] => 10753048 [patent_doc_number] => 20160099200 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-04-07 [patent_title] => 'ALUMINUM ALLOY LEAD FRAME FOR A SEMICONDUCTOR DEVICE AND CORRESPONDING MANUFACTURING PROCESS' [patent_app_type] => utility [patent_app_number] => 14/750920 [patent_app_country] => US [patent_app_date] => 2015-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3084 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14750920 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/750920
ALUMINUM ALLOY LEAD FRAME FOR A SEMICONDUCTOR DEVICE AND CORRESPONDING MANUFACTURING PROCESS Jun 24, 2015 Abandoned
Array ( [id] => 10984240 [patent_doc_number] => 20160181185 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-06-23 [patent_title] => 'SEMICONDUCTOR PACKAGE STRUCTURE' [patent_app_type] => utility [patent_app_number] => 14/747641 [patent_app_country] => US [patent_app_date] => 2015-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2207 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14747641 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/747641
Semiconductor package structure Jun 22, 2015 Issued
Array ( [id] => 12089062 [patent_doc_number] => 09842796 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-12-12 [patent_title] => 'Electronic module including a device for dissipating heat generated by a semiconductor unit situated in a plastic housing and method for manufacturing an electronic module' [patent_app_type] => utility [patent_app_number] => 15/317140 [patent_app_country] => US [patent_app_date] => 2015-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 4510 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15317140 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/317140
Electronic module including a device for dissipating heat generated by a semiconductor unit situated in a plastic housing and method for manufacturing an electronic module Jun 7, 2015 Issued
Array ( [id] => 11802374 [patent_doc_number] => 09543275 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-01-10 [patent_title] => 'Semiconductor package with a lead, package-on-package device including the same, and mobile device including the same' [patent_app_type] => utility [patent_app_number] => 14/732653 [patent_app_country] => US [patent_app_date] => 2015-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 16 [patent_no_of_words] => 8541 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14732653 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/732653
Semiconductor package with a lead, package-on-package device including the same, and mobile device including the same Jun 4, 2015 Issued
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