Search

Alexander O Williams

Examiner (ID: 12148, Phone: (571)272-1924 , Office: P/2826 )

Most Active Art Unit
2826
Art Unit(s)
2826, 2811, 2508
Total Applications
2764
Issued Applications
2318
Pending Applications
64
Abandoned Applications
383

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 10402689 [patent_doc_number] => 20150287698 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-10-08 [patent_title] => 'SEMICONDUCTOR ASSEMBLY COMPRISING CHIP ARRAYS' [patent_app_type] => utility [patent_app_number] => 14/669208 [patent_app_country] => US [patent_app_date] => 2015-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6473 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14669208 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/669208
Semiconductor assembly comprising chip arrays Mar 25, 2015 Issued
Array ( [id] => 11333665 [patent_doc_number] => 09524917 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-12-20 [patent_title] => 'Chip level heat dissipation using silicon' [patent_app_type] => utility [patent_app_number] => 14/662088 [patent_app_country] => US [patent_app_date] => 2015-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 38 [patent_figures_cnt] => 41 [patent_no_of_words] => 5037 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14662088 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/662088
Chip level heat dissipation using silicon Mar 17, 2015 Issued
Array ( [id] => 10385210 [patent_doc_number] => 20150270217 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-09-24 [patent_title] => 'POWER MODULE PACKAGE' [patent_app_type] => utility [patent_app_number] => 14/661844 [patent_app_country] => US [patent_app_date] => 2015-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3550 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14661844 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/661844
Power module package including heat spreader and inductance coil Mar 17, 2015 Issued
Array ( [id] => 11187543 [patent_doc_number] => 09418954 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-08-16 [patent_title] => 'Integrated circuit chip assembled on an interposer' [patent_app_type] => utility [patent_app_number] => 14/659680 [patent_app_country] => US [patent_app_date] => 2015-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 13 [patent_no_of_words] => 3676 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14659680 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/659680
Integrated circuit chip assembled on an interposer Mar 16, 2015 Issued
Array ( [id] => 11524538 [patent_doc_number] => 09607949 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-03-28 [patent_title] => 'Semiconductor device having semiconductor chips in resin and electronic circuit device with the semiconductor device' [patent_app_type] => utility [patent_app_number] => 14/641864 [patent_app_country] => US [patent_app_date] => 2015-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 25 [patent_no_of_words] => 7506 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14641864 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/641864
Semiconductor device having semiconductor chips in resin and electronic circuit device with the semiconductor device Mar 8, 2015 Issued
Array ( [id] => 11894507 [patent_doc_number] => 09764430 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-09-19 [patent_title] => 'Lead-free solder alloy, solder material and joined structure' [patent_app_type] => utility [patent_app_number] => 15/120937 [patent_app_country] => US [patent_app_date] => 2015-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 4142 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 36 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15120937 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/120937
Lead-free solder alloy, solder material and joined structure Feb 18, 2015 Issued
Array ( [id] => 11694423 [patent_doc_number] => 20170170141 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-15 [patent_title] => 'METHOD FOR ARRANGING ELECTRONIC SWITCHING ELEMENTS, ELECTRONIC SWITCHING ARRANGEMENT AND USE OF A CARRIER HAVING A BONDING LAYER' [patent_app_type] => utility [patent_app_number] => 15/115541 [patent_app_country] => US [patent_app_date] => 2015-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6064 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15115541 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/115541
Method for arranging electronic switching elements, electronic switching arrangement and use of a carrier having a bonding layer Jan 27, 2015 Issued
Array ( [id] => 13111855 [patent_doc_number] => 10074585 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-09-11 [patent_title] => Power module with dummy terminal structure [patent_app_type] => utility [patent_app_number] => 15/529568 [patent_app_country] => US [patent_app_date] => 2015-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 2260 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15529568 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/529568
Power module with dummy terminal structure Jan 19, 2015 Issued
Array ( [id] => 11959399 [patent_doc_number] => 20170263551 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-09-14 [patent_title] => 'NOVEL METHOD FOR CREATING ALTERNATE HARDMASK CAP INTERCONNECT STRUCTURE WITH INCREASED OVERLAY MARGIN' [patent_app_type] => utility [patent_app_number] => 15/529483 [patent_app_country] => US [patent_app_date] => 2014-12-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 12036 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15529483 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/529483
Method for creating alternate hardmask cap interconnect structure with increased overlay margin Dec 23, 2014 Issued
Array ( [id] => 11959401 [patent_doc_number] => 20170263553 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-09-14 [patent_title] => 'STRUCTURE AND METHOD TO SELF ALIGN VIA TO TOP AND BOTTOM OF TIGHT PITCH METAL INTERCONNECT LAYERS' [patent_app_type] => utility [patent_app_number] => 15/529484 [patent_app_country] => US [patent_app_date] => 2014-12-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 9694 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15529484 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/529484
Structure and method to self align via to top and bottom of tight pitch metal interconnect layers Dec 23, 2014 Issued
Array ( [id] => 13019053 [patent_doc_number] => 10032643 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-07-24 [patent_title] => Method and structure to contact tight pitch conductive layers with guided vias using alternating hardmasks and encapsulating etchstop liner scheme [patent_app_type] => utility [patent_app_number] => 15/528736 [patent_app_country] => US [patent_app_date] => 2014-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 42 [patent_no_of_words] => 10745 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15528736 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/528736
Method and structure to contact tight pitch conductive layers with guided vias using alternating hardmasks and encapsulating etchstop liner scheme Dec 21, 2014 Issued
Array ( [id] => 10217495 [patent_doc_number] => 20150102488 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-04-16 [patent_title] => 'PRINTED CIRCUIT BOARD USING SOLDER COATING BALL' [patent_app_type] => utility [patent_app_number] => 14/575915 [patent_app_country] => US [patent_app_date] => 2014-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4534 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14575915 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/575915
PRINTED CIRCUIT BOARD USING SOLDER COATING BALL Dec 17, 2014 Abandoned
Array ( [id] => 10199213 [patent_doc_number] => 20150084199 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-03-26 [patent_title] => 'Copper Ball Bond Features and Structure' [patent_app_type] => utility [patent_app_number] => 14/557769 [patent_app_country] => US [patent_app_date] => 2014-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 12588 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14557769 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/557769
Copper ball bond features and structure Dec 1, 2014 Issued
Array ( [id] => 11564772 [patent_doc_number] => 09627367 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-04-18 [patent_title] => 'Memory devices with controllers under memory packages and associated systems and methods' [patent_app_type] => utility [patent_app_number] => 14/550243 [patent_app_country] => US [patent_app_date] => 2014-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 4723 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14550243 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/550243
Memory devices with controllers under memory packages and associated systems and methods Nov 20, 2014 Issued
Array ( [id] => 9928395 [patent_doc_number] => 20150076587 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-03-19 [patent_title] => 'NONVOLATILE MEMORY DEVICES HAVING A THREE DIMENSIONAL STRUCTURE' [patent_app_type] => utility [patent_app_number] => 14/548557 [patent_app_country] => US [patent_app_date] => 2014-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 5109 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14548557 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/548557
Nonvolatile memory devices having a three dimensional structure utilizing strapping of a common source region and/or a well region Nov 19, 2014 Issued
Array ( [id] => 11459987 [patent_doc_number] => 20170053893 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-02-23 [patent_title] => 'Semiconductor Device and Method for Producing Semiconductor Device' [patent_app_type] => utility [patent_app_number] => 15/039083 [patent_app_country] => US [patent_app_date] => 2014-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4802 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15039083 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/039083
Semiconductor device having wire formed with loop portion and method for producing the semiconductor device Nov 18, 2014 Issued
Array ( [id] => 11710492 [patent_doc_number] => 20170178991 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-22 [patent_title] => 'METHOD FOR PRODUCING ELECTRONIC DEVICES' [patent_app_type] => utility [patent_app_number] => 15/036641 [patent_app_country] => US [patent_app_date] => 2014-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5453 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15036641 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/036641
METHOD FOR PRODUCING ELECTRONIC DEVICES Nov 12, 2014 Abandoned
Array ( [id] => 11599776 [patent_doc_number] => 09646953 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-05-09 [patent_title] => 'Integrated circuit packaging techniques and configurations for small form-factor or wearable devices' [patent_app_type] => utility [patent_app_number] => 14/775550 [patent_app_country] => US [patent_app_date] => 2014-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 24 [patent_no_of_words] => 8307 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14775550 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/775550
Integrated circuit packaging techniques and configurations for small form-factor or wearable devices Nov 11, 2014 Issued
Array ( [id] => 11909879 [patent_doc_number] => 09778688 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-10-03 [patent_title] => 'Flexible system-in-package solutions for wearable devices' [patent_app_type] => utility [patent_app_number] => 14/779300 [patent_app_country] => US [patent_app_date] => 2014-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 14 [patent_no_of_words] => 8227 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14779300 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/779300
Flexible system-in-package solutions for wearable devices Nov 11, 2014 Issued
Array ( [id] => 10826091 [patent_doc_number] => 20160172259 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-06-16 [patent_title] => 'CUSTOMIZED MODULE LID' [patent_app_type] => utility [patent_app_number] => 14/535391 [patent_app_country] => US [patent_app_date] => 2014-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 5990 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14535391 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/535391
Customized module lid Nov 6, 2014 Issued
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