Search

Alexander O Williams

Examiner (ID: 4421, Phone: (571)272-1924 , Office: P/2826 )

Most Active Art Unit
2826
Art Unit(s)
2508, 2826, 2811
Total Applications
2764
Issued Applications
2318
Pending Applications
64
Abandoned Applications
383

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 10525557 [patent_doc_number] => 09252077 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-02-02 [patent_title] => 'Package vias for radio frequency antenna connections' [patent_app_type] => utility [patent_app_number] => 14/037213 [patent_app_country] => US [patent_app_date] => 2013-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 15 [patent_no_of_words] => 6448 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14037213 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/037213
Package vias for radio frequency antenna connections Sep 24, 2013 Issued
Array ( [id] => 10125324 [patent_doc_number] => 09159690 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-10-13 [patent_title] => 'Tall solders for through-mold interconnect' [patent_app_type] => utility [patent_app_number] => 14/036755 [patent_app_country] => US [patent_app_date] => 2013-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 41 [patent_no_of_words] => 6214 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 292 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14036755 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/036755
Tall solders for through-mold interconnect Sep 24, 2013 Issued
Array ( [id] => 10066754 [patent_doc_number] => 09105612 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-08-11 [patent_title] => 'Microelectronic packages having cavities for receiving microelectronic elements' [patent_app_type] => utility [patent_app_number] => 14/034265 [patent_app_country] => US [patent_app_date] => 2013-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 56 [patent_figures_cnt] => 125 [patent_no_of_words] => 24779 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14034265 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/034265
Microelectronic packages having cavities for receiving microelectronic elements Sep 22, 2013 Issued
Array ( [id] => 10531232 [patent_doc_number] => 09257372 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-02-09 [patent_title] => 'Surface mount package for a semiconductor integrated device, related assembly and manufacturing process' [patent_app_type] => utility [patent_app_number] => 14/032075 [patent_app_country] => US [patent_app_date] => 2013-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 12 [patent_no_of_words] => 3257 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14032075 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/032075
Surface mount package for a semiconductor integrated device, related assembly and manufacturing process Sep 18, 2013 Issued
Array ( [id] => 10178951 [patent_doc_number] => 09209164 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-12-08 [patent_title] => 'Interconnection structure of package structure and method of forming the same' [patent_app_type] => utility [patent_app_number] => 14/020045 [patent_app_country] => US [patent_app_date] => 2013-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 26 [patent_no_of_words] => 6951 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14020045 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/020045
Interconnection structure of package structure and method of forming the same Sep 5, 2013 Issued
Array ( [id] => 10184753 [patent_doc_number] => 09214434 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-12-15 [patent_title] => 'Fan-out semiconductor package' [patent_app_type] => utility [patent_app_number] => 14/017802 [patent_app_country] => US [patent_app_date] => 2013-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 27 [patent_no_of_words] => 4742 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14017802 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/017802
Fan-out semiconductor package Sep 3, 2013 Issued
Array ( [id] => 10531195 [patent_doc_number] => 09257335 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-02-09 [patent_title] => 'Electronic devices utilizing contact pads with protrusions and methods for fabrication' [patent_app_type] => utility [patent_app_number] => 14/426302 [patent_app_country] => US [patent_app_date] => 2013-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 5319 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14426302 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/426302
Electronic devices utilizing contact pads with protrusions and methods for fabrication Sep 3, 2013 Issued
Array ( [id] => 10053689 [patent_doc_number] => 09093575 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-07-28 [patent_title] => 'Semiconductor device and solid-state imaging device with tantalum oxide layer formed by diffusing a material of an electrode of necessity or a counter electrode' [patent_app_type] => utility [patent_app_number] => 14/017816 [patent_app_country] => US [patent_app_date] => 2013-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 47 [patent_figures_cnt] => 73 [patent_no_of_words] => 22193 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 242 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14017816 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/017816
Semiconductor device and solid-state imaging device with tantalum oxide layer formed by diffusing a material of an electrode of necessity or a counter electrode Sep 3, 2013 Issued
Array ( [id] => 10053270 [patent_doc_number] => 09093150 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-07-28 [patent_title] => 'Multi-chip packaged integrated circuit with flash memory and slave memory controller' [patent_app_type] => utility [patent_app_number] => 14/016224 [patent_app_country] => US [patent_app_date] => 2013-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 17 [patent_no_of_words] => 14477 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14016224 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/016224
Multi-chip packaged integrated circuit with flash memory and slave memory controller Sep 2, 2013 Issued
Array ( [id] => 9832412 [patent_doc_number] => 08941230 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-01-27 [patent_title] => 'Semiconductor package and manufacturing method' [patent_app_type] => utility [patent_app_number] => 14/010245 [patent_app_country] => US [patent_app_date] => 2013-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 56 [patent_no_of_words] => 22488 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 298 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14010245 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/010245
Semiconductor package and manufacturing method Aug 25, 2013 Issued
Array ( [id] => 10093117 [patent_doc_number] => 09129947 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-09-08 [patent_title] => 'Multi-chip packaging structure and method' [patent_app_type] => utility [patent_app_number] => 13/973132 [patent_app_country] => US [patent_app_date] => 2013-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4456 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 228 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13973132 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/973132
Multi-chip packaging structure and method Aug 21, 2013 Issued
Array ( [id] => 9455858 [patent_doc_number] => 08716872 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-05-06 [patent_title] => 'Stacked semiconductor package including connections electrically connecting first and second semiconductor packages' [patent_app_type] => utility [patent_app_number] => 13/970071 [patent_app_country] => US [patent_app_date] => 2013-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 30 [patent_no_of_words] => 13587 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13970071 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/970071
Stacked semiconductor package including connections electrically connecting first and second semiconductor packages Aug 18, 2013 Issued
Array ( [id] => 9303942 [patent_doc_number] => 20140042617 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-02-13 [patent_title] => 'SEMICONDUCTOR DEVICE HAVING PENETRATION ELECTRODE' [patent_app_type] => utility [patent_app_number] => 13/961225 [patent_app_country] => US [patent_app_date] => 2013-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 3487 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13961225 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/961225
SEMICONDUCTOR DEVICE HAVING PENETRATION ELECTRODE Aug 6, 2013 Abandoned
Array ( [id] => 9291498 [patent_doc_number] => 20140035132 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-02-06 [patent_title] => 'SURFACE MOUNT CHIP' [patent_app_type] => utility [patent_app_number] => 13/955325 [patent_app_country] => US [patent_app_date] => 2013-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2543 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13955325 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/955325
SURFACE MOUNT CHIP Jul 30, 2013 Abandoned
Array ( [id] => 9542590 [patent_doc_number] => 20140167237 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-06-19 [patent_title] => 'POWER MODULE PACKAGE' [patent_app_type] => utility [patent_app_number] => 13/950205 [patent_app_country] => US [patent_app_date] => 2013-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3800 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13950205 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/950205
POWER MODULE PACKAGE Jul 23, 2013 Abandoned
Array ( [id] => 9266687 [patent_doc_number] => 20140021603 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-01-23 [patent_title] => 'USING AN INTERCONNECT BUMP TO TRAVERSE THROUGH A PASSIVATION LAYER OF A SEMICONDUCTOR DIE' [patent_app_type] => utility [patent_app_number] => 13/948516 [patent_app_country] => US [patent_app_date] => 2013-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 5372 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13948516 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/948516
USING AN INTERCONNECT BUMP TO TRAVERSE THROUGH A PASSIVATION LAYER OF A SEMICONDUCTOR DIE Jul 22, 2013 Abandoned
Array ( [id] => 10010563 [patent_doc_number] => 09054089 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-06-09 [patent_title] => 'Lead frame package having discharge holes and method of manufacturing the same' [patent_app_type] => utility [patent_app_number] => 13/949186 [patent_app_country] => US [patent_app_date] => 2013-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 4443 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13949186 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/949186
Lead frame package having discharge holes and method of manufacturing the same Jul 22, 2013 Issued
Array ( [id] => 9303934 [patent_doc_number] => 20140042608 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-02-13 [patent_title] => 'SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 13/935475 [patent_app_country] => US [patent_app_date] => 2013-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 14724 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13935475 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/935475
SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME Jul 2, 2013 Abandoned
Array ( [id] => 9202448 [patent_doc_number] => 20140001624 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-01-02 [patent_title] => 'AIR CAVITY PACKAGES HAVING HIGH THERMAL CONDUCTIVITY BASE PLATES AND METHODS OF MAKING' [patent_app_type] => utility [patent_app_number] => 13/930105 [patent_app_country] => US [patent_app_date] => 2013-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2254 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13930105 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/930105
Semiconductor packages having metal composite base plates Jun 27, 2013 Issued
Array ( [id] => 10145084 [patent_doc_number] => 09177897 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-11-03 [patent_title] => 'Integrated circuit packaging system with trace protection layer and method of manufacture thereof' [patent_app_type] => utility [patent_app_number] => 13/930319 [patent_app_country] => US [patent_app_date] => 2013-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 30 [patent_no_of_words] => 11467 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13930319 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/930319
Integrated circuit packaging system with trace protection layer and method of manufacture thereof Jun 27, 2013 Issued
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