Search

Alexander O. Williams

Examiner (ID: 4421)

Most Active Art Unit
2826
Art Unit(s)
2508, 2826, 2811
Total Applications
2764
Issued Applications
2318
Pending Applications
64
Abandoned Applications
383

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 8863335 [patent_doc_number] => 20130147038 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-06-13 [patent_title] => 'SEMICONDUCTOR DEVICE INCLUDING STACKED SEMICONDUCTOR CHIPS WITHOUT OCCURRING OF CRACK' [patent_app_type] => utility [patent_app_number] => 13/706752 [patent_app_country] => US [patent_app_date] => 2012-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 6463 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13706752 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/706752
Semiconductor device including stacked semiconductor chips without occurring of crack Dec 5, 2012 Issued
Array ( [id] => 8925574 [patent_doc_number] => 20130181334 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-07-18 [patent_title] => 'CONNECTOR AND RESIN-SEALED SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 13/706699 [patent_app_country] => US [patent_app_date] => 2012-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3282 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13706699 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/706699
Connector and resin-sealed semiconductor device Dec 5, 2012 Issued
Array ( [id] => 8888625 [patent_doc_number] => 20130161809 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-06-27 [patent_title] => 'SUBSTRATE STRUCTURE, SEMICONDUCTOR PACKAGE DEVICE, AND MANUFACTURING METHOD OF SUBSTRATE STRUCTURE' [patent_app_type] => utility [patent_app_number] => 13/689207 [patent_app_country] => US [patent_app_date] => 2012-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 5881 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13689207 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/689207
Substrate structure, semiconductor package device, and manufacturing method of substrate structure Nov 28, 2012 Issued
Array ( [id] => 8742684 [patent_doc_number] => 20130082402 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-04-04 [patent_title] => 'SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 13/687572 [patent_app_country] => US [patent_app_date] => 2012-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 9703 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13687572 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/687572
SEMICONDUCTOR DEVICE Nov 27, 2012 Abandoned
Array ( [id] => 11776146 [patent_doc_number] => 09385098 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-07-05 [patent_title] => 'Variable-size solder bump structures for integrated circuit packaging' [patent_app_type] => utility [patent_app_number] => 13/683315 [patent_app_country] => US [patent_app_date] => 2012-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 4273 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13683315 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/683315
Variable-size solder bump structures for integrated circuit packaging Nov 20, 2012 Issued
Array ( [id] => 8851017 [patent_doc_number] => 20130140692 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-06-06 [patent_title] => 'WIRING SUBSTRATE, MANUFACTURING METHOD OF WIRING SUBSTRATE, AND SEMICONDUCTOR PACKAGE INCLUDING WIRING SUBSTRATE' [patent_app_type] => utility [patent_app_number] => 13/681732 [patent_app_country] => US [patent_app_date] => 2012-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 12284 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13681732 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/681732
Wiring substrate including projecting part having electrode pad formed thereon Nov 19, 2012 Issued
Array ( [id] => 8825993 [patent_doc_number] => 20130127038 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-05-23 [patent_title] => 'SEMICONDUCTOR DEVICE BONDED BY AN ANISOTROPIC CONDUCTIVE FILM' [patent_app_type] => utility [patent_app_number] => 13/679113 [patent_app_country] => US [patent_app_date] => 2012-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7121 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13679113 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/679113
Semiconductor device bonded by an anisotropic conductive film Nov 15, 2012 Issued
Array ( [id] => 9850800 [patent_doc_number] => 08952537 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-02-10 [patent_title] => 'Conductive bump structure with a plurality of metal layers' [patent_app_type] => utility [patent_app_number] => 13/677904 [patent_app_country] => US [patent_app_date] => 2012-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 13 [patent_no_of_words] => 3216 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13677904 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/677904
Conductive bump structure with a plurality of metal layers Nov 14, 2012 Issued
Array ( [id] => 9474403 [patent_doc_number] => 20140131866 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-05-15 [patent_title] => 'TRACE ROUTING WITHIN A SEMICONDUCTOR PACKAGE SUBSTRATE' [patent_app_type] => utility [patent_app_number] => 13/675008 [patent_app_country] => US [patent_app_date] => 2012-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4183 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13675008 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/675008
Trace routing within a semiconductor package substrate Nov 12, 2012 Issued
Array ( [id] => 10125333 [patent_doc_number] => 09159699 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-10-13 [patent_title] => 'Interconnection structure having a via structure' [patent_app_type] => utility [patent_app_number] => 13/675297 [patent_app_country] => US [patent_app_date] => 2012-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 2607 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13675297 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/675297
Interconnection structure having a via structure Nov 12, 2012 Issued
Array ( [id] => 9474411 [patent_doc_number] => 20140131875 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-05-15 [patent_title] => 'Z-CONNECTION USING ELECTROLESS PLATING' [patent_app_type] => utility [patent_app_number] => 13/675445 [patent_app_country] => US [patent_app_date] => 2012-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6767 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13675445 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/675445
Z-connection using electroless plating Nov 12, 2012 Issued
Array ( [id] => 9474391 [patent_doc_number] => 20140131854 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-05-15 [patent_title] => 'MULTI-CHIP MODULE CONNECTION BY WAY OF BRIDGING BLOCKS' [patent_app_type] => utility [patent_app_number] => 13/675184 [patent_app_country] => US [patent_app_date] => 2012-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3288 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13675184 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/675184
MULTI-CHIP MODULE CONNECTION BY WAY OF BRIDGING BLOCKS Nov 12, 2012 Abandoned
Array ( [id] => 9474430 [patent_doc_number] => 20140131894 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-05-15 [patent_title] => 'POP Structures with Air Gaps and Methods for Forming the Same' [patent_app_type] => utility [patent_app_number] => 13/675628 [patent_app_country] => US [patent_app_date] => 2012-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 2853 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13675628 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/675628
POP structures with dams encircling air gaps and methods for forming the same Nov 12, 2012 Issued
Array ( [id] => 9621403 [patent_doc_number] => 08791578 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-07-29 [patent_title] => 'Through-silicon via structure with patterned surface, patterned sidewall and local isolation' [patent_app_type] => utility [patent_app_number] => 13/674096 [patent_app_country] => US [patent_app_date] => 2012-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 8 [patent_no_of_words] => 4487 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13674096 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/674096
Through-silicon via structure with patterned surface, patterned sidewall and local isolation Nov 11, 2012 Issued
Array ( [id] => 8818490 [patent_doc_number] => 20130119535 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-05-16 [patent_title] => 'FLIP CHIP PACKAGES WITH IMPROVED THERMAL PERFORMANCE' [patent_app_type] => utility [patent_app_number] => 13/674813 [patent_app_country] => US [patent_app_date] => 2012-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4814 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13674813 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/674813
Flip chip packages with improved thermal performance Nov 11, 2012 Issued
Array ( [id] => 8960929 [patent_doc_number] => 20130200531 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-08-08 [patent_title] => 'Circuit Board, Method for Fabricating the Same and Semiconductor Package Using the Same' [patent_app_type] => utility [patent_app_number] => 13/674331 [patent_app_country] => US [patent_app_date] => 2012-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8635 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13674331 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/674331
Circuit board, comprising a core insulation film Nov 11, 2012 Issued
Array ( [id] => 8914081 [patent_doc_number] => 20130175706 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-07-11 [patent_title] => 'SEMICONDUCTOR PACKAGE' [patent_app_type] => utility [patent_app_number] => 13/672898 [patent_app_country] => US [patent_app_date] => 2012-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 8335 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13672898 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/672898
Semiconductor package including a semiconductor chip with a through silicon via Nov 8, 2012 Issued
Array ( [id] => 9474437 [patent_doc_number] => 20140131900 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-05-15 [patent_title] => 'MICROELECTRONIC ASSEMBLY WITH THERMALLY AND ELECTRICALLY CONDUCTIVE UNDERFILL' [patent_app_type] => utility [patent_app_number] => 13/672750 [patent_app_country] => US [patent_app_date] => 2012-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5701 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13672750 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/672750
Microelectronic assembly with thermally and electrically conductive underfill Nov 8, 2012 Issued
Array ( [id] => 9474413 [patent_doc_number] => 20140131877 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-05-15 [patent_title] => 'STRESS RELIEF STRUCTURES IN PACKAGE ASSEMBLIES' [patent_app_type] => utility [patent_app_number] => 13/673703 [patent_app_country] => US [patent_app_date] => 2012-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2999 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13673703 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/673703
Stress relief structures in package assemblies Nov 8, 2012 Issued
Array ( [id] => 11483645 [patent_doc_number] => 09590209 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-03-07 [patent_title] => 'Mirror device' [patent_app_type] => utility [patent_app_number] => 14/440697 [patent_app_country] => US [patent_app_date] => 2012-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 6850 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14440697 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/440697
Mirror device Nov 7, 2012 Issued
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