
Alexander O. Williams
Examiner (ID: 4421)
| Most Active Art Unit | 2826 |
| Art Unit(s) | 2508, 2826, 2811 |
| Total Applications | 2764 |
| Issued Applications | 2318 |
| Pending Applications | 64 |
| Abandoned Applications | 383 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 9389967
[patent_doc_number] => 08686571
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2014-04-01
[patent_title] => 'Bonding layer structure and method for wafer to wafer bonding'
[patent_app_type] => utility
[patent_app_number] => 13/571260
[patent_app_country] => US
[patent_app_date] => 2012-08-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 4
[patent_no_of_words] => 2684
[patent_no_of_claims] => 14
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[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13571260
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/571260 | Bonding layer structure and method for wafer to wafer bonding | Aug 8, 2012 | Issued |
Array
(
[id] => 9965412
[patent_doc_number] => 09013029
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2015-04-21
[patent_title] => 'Joined body having an anti-corrosion film formed around a junction portion, and a semiconductor device having the same'
[patent_app_type] => utility
[patent_app_number] => 13/882436
[patent_app_country] => US
[patent_app_date] => 2012-08-08
[patent_effective_date] => 0000-00-00
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[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13882436
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/882436 | Joined body having an anti-corrosion film formed around a junction portion, and a semiconductor device having the same | Aug 7, 2012 | Issued |
Array
(
[id] => 8777405
[patent_doc_number] => 20130099380
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-04-25
[patent_title] => 'WAFER LEVEL CHIP SCALE PACKAGE DEVICE AND MANUFACTURING METHOD THEROF'
[patent_app_type] => utility
[patent_app_number] => 13/569729
[patent_app_country] => US
[patent_app_date] => 2012-08-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/569729 | WAFER LEVEL CHIP SCALE PACKAGE DEVICE AND MANUFACTURING METHOD THEROF | Aug 7, 2012 | Abandoned |
Array
(
[id] => 8863359
[patent_doc_number] => 20130147062
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-06-13
[patent_title] => 'MULTI-CHIP PACKAGE AND METHOD OF MANUFACTURING THE SAME'
[patent_app_type] => utility
[patent_app_number] => 13/567046
[patent_app_country] => US
[patent_app_date] => 2012-08-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/567046 | Multi-chip package with a supporting member and method of manufacturing the same | Aug 3, 2012 | Issued |
Array
(
[id] => 10099842
[patent_doc_number] => 09136160
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2015-09-15
[patent_title] => 'Solid hole array and method for forming the same'
[patent_app_type] => utility
[patent_app_number] => 13/697372
[patent_app_country] => US
[patent_app_date] => 2012-07-31
[patent_effective_date] => 0000-00-00
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[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13697372
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/697372 | Solid hole array and method for forming the same | Jul 30, 2012 | Issued |
Array
(
[id] => 9441546
[patent_doc_number] => 08710660
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2014-04-29
[patent_title] => 'Hybrid interconnect scheme including aluminum metal line in low-k dielectric'
[patent_app_type] => utility
[patent_app_number] => 13/554817
[patent_app_country] => US
[patent_app_date] => 2012-07-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/554817 | Hybrid interconnect scheme including aluminum metal line in low-k dielectric | Jul 19, 2012 | Issued |
Array
(
[id] => 9286858
[patent_doc_number] => 08643189
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2014-02-04
[patent_title] => 'Packaged semiconductor die with power rail pads'
[patent_app_type] => utility
[patent_app_number] => 13/550627
[patent_app_country] => US
[patent_app_date] => 2012-07-17
[patent_effective_date] => 0000-00-00
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/550627 | Packaged semiconductor die with power rail pads | Jul 16, 2012 | Issued |
Array
(
[id] => 9504259
[patent_doc_number] => 08742577
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2014-06-03
[patent_title] => 'Semiconductor package having an anti-contact layer'
[patent_app_type] => utility
[patent_app_number] => 13/550949
[patent_app_country] => US
[patent_app_date] => 2012-07-17
[patent_effective_date] => 0000-00-00
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[patent_no_of_words] => 8337
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[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13550949
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/550949 | Semiconductor package having an anti-contact layer | Jul 16, 2012 | Issued |
Array
(
[id] => 8615409
[patent_doc_number] => 20130020721
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-01-24
[patent_title] => 'SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME'
[patent_app_type] => utility
[patent_app_number] => 13/549789
[patent_app_country] => US
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/549789 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME | Jul 15, 2012 | Abandoned |
Array
(
[id] => 10845167
[patent_doc_number] => 08872347
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2014-10-28
[patent_title] => 'Semiconductor device having groove-shaped via-hole'
[patent_app_type] => utility
[patent_app_number] => 13/548857
[patent_app_country] => US
[patent_app_date] => 2012-07-13
[patent_effective_date] => 0000-00-00
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/548857 | Semiconductor device having groove-shaped via-hole | Jul 12, 2012 | Issued |
Array
(
[id] => 8480990
[patent_doc_number] => 20120280396
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[patent_kind] => A1
[patent_issue_date] => 2012-11-08
[patent_title] => 'SEMICONDUCTOR DEVICE HAVING GROOVE-SHAPED VIA-HOLE'
[patent_app_type] => utility
[patent_app_number] => 13/548911
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/548911 | Semiconductor device having groove-shaped via-hole | Jul 12, 2012 | Issued |
Array
(
[id] => 9704611
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[patent_title] => 'Semiconductor device having groove-shaped via-hole'
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Array
(
[id] => 8474562
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[patent_title] => 'SEMICONDUCTOR DEVICE HAVING GROOVE-SHAPED VIA-HOLE'
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Array
(
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Array
(
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Array
(
[id] => 9441541
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[patent_title] => 'Die packages and systems having the die packages'
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Array
(
[id] => 9590035
[patent_doc_number] => 08779578
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[patent_kind] => B2
[patent_issue_date] => 2014-07-15
[patent_title] => 'Multi-chip socket'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/537404 | Multi-chip socket | Jun 28, 2012 | Issued |
Array
(
[id] => 8404989
[patent_doc_number] => 20120237046
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[patent_issue_date] => 2012-09-20
[patent_title] => 'INTERCOM HEADSET CONNECTION AND DISCONNECTION RESPONSES'
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Array
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Array
(
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/478482 | Nonvolatile memory devices having a three dimensional structure | May 22, 2012 | Issued |