Alexander O. Williams

Array ( [id] => 9590034 [patent_doc_number] => 08779577 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-07-15 [patent_title] => 'Semiconductor chip comprising a plurality of contact pads and a plurality of associated pad cells' [patent_app_type] => utility [patent_app_number] => 13/371853 [patent_app_country] => US [patent_app_date] => 2012-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 16 [patent_no_of_words] => 10832 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13371853 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8973835 [patent_doc_number] => 20130207265 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-08-15 [patent_title] => 'STRUCTURE AND METHOD OF MAKING THE SAME' [patent_app_type] => utility [patent_app_number] => 13/370828 [patent_app_country] => US [patent_app_date] => 2012-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4240 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13370828 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9127810 [patent_doc_number] => 08575761 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-11-05 [patent_title] => 'Segmented supply rail configuration for a digital integrated circuit' [patent_app_type] => utility [patent_app_number] => 13/370374 [patent_app_country] => US [patent_app_date] => 2012-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 2145 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13370374 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9711559 [patent_doc_number] => 08836135 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-09-16 [patent_title] => 'Semiconductor device with interconnection connecting to a via' [patent_app_type] => utility [patent_app_number] => 13/370723 [patent_app_country] => US [patent_app_date] => 2012-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 22 [patent_no_of_words] => 5043 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13370723 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8973834 [patent_doc_number] => 20130207264 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-08-15 [patent_title] => 'Stress Reduction Apparatus' [patent_app_type] => utility [patent_app_number] => 13/370161 [patent_app_country] => US [patent_app_date] => 2012-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2875 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13370161 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8995659 [patent_doc_number] => 08519546 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-08-27 [patent_title] => 'Stacked multi-die electronic device with interposed electrically conductive strap' [patent_app_type] => utility [patent_app_number] => 13/369803 [patent_app_country] => US [patent_app_date] => 2012-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3851 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13369803 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8960933 [patent_doc_number] => 20130200535 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-08-08 [patent_title] => 'OVERLAY MARK FOR MULTIPLE PRE-LAYERS AND CURRENTLY LAYER' [patent_app_type] => utility [patent_app_number] => 13/366622 [patent_app_country] => US [patent_app_date] => 2012-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2137 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13366622 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8344874 [patent_doc_number] => 20120205798 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-08-16 [patent_title] => 'SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 13/365473 [patent_app_country] => US [patent_app_date] => 2012-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3335 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13365473 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9763055 [patent_doc_number] => 08847383 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-09-30 [patent_title] => 'Integrated circuit package strip with stiffener' [patent_app_type] => utility [patent_app_number] => 13/363620 [patent_app_country] => US [patent_app_date] => 2012-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 15 [patent_no_of_words] => 5554 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13363620 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9429673 [patent_doc_number] => 08705756 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-04-22 [patent_title] => 'Distributed audio system' [patent_app_type] => utility [patent_app_number] => 13/336161 [patent_app_country] => US [patent_app_date] => 2011-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3632 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13336161 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10851681 [patent_doc_number] => 08878367 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-11-04 [patent_title] => 'Substrate structure with through vias' [patent_app_type] => utility [patent_app_number] => 13/303208 [patent_app_country] => US [patent_app_date] => 2011-11-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 3822 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13303208 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9127809 [patent_doc_number] => 08575760 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-11-05 [patent_title] => 'Semiconductor devices having electrodes' [patent_app_type] => utility [patent_app_number] => 13/303255 [patent_app_country] => US [patent_app_date] => 2011-11-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 48 [patent_figures_cnt] => 53 [patent_no_of_words] => 13769 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13303255 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9850792 [patent_doc_number] => 08952529 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-02-10 [patent_title] => 'Semiconductor device with conductive layer over substrate with vents to channel bump material and reduce interconnect voids' [patent_app_type] => utility [patent_app_number] => 13/303019 [patent_app_country] => US [patent_app_date] => 2011-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 38 [patent_no_of_words] => 7143 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 36 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13303019 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8995633 [patent_doc_number] => 08519520 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-08-27 [patent_title] => 'Semiconductor package of small footprint with a stack of lead frame die paddle sandwich between high-side and low-side MOSFETs and manufacturing method' [patent_app_type] => utility [patent_app_number] => 13/302077 [patent_app_country] => US [patent_app_date] => 2011-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 2102 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 222 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13302077 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8825986 [patent_doc_number] => 20130127031 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-05-23 [patent_title] => 'CHIP-CARRIER, A METHOD FOR FORMING A CHIP-CARRIER AND A METHOD FOR FORMING A CHIP PACKAGE' [patent_app_type] => utility [patent_app_number] => 13/301823 [patent_app_country] => US [patent_app_date] => 2011-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7089 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13301823 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8321366 [patent_doc_number] => 20120193780 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-08-02 [patent_title] => 'SEMICONDUCTOR MOUNTING DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR MOUNTING DEVICE' [patent_app_type] => utility [patent_app_number] => 13/302572 [patent_app_country] => US [patent_app_date] => 2011-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 4726 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13302572 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9074976 [patent_doc_number] => 08552556 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-10-08 [patent_title] => 'Wafer level fan out package' [patent_app_type] => utility [patent_app_number] => 13/302501 [patent_app_country] => US [patent_app_date] => 2011-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 27 [patent_no_of_words] => 4702 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13302501 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8680936 [patent_doc_number] => 20130049220 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-02-28 [patent_title] => 'Through Silicon Via Keep Out Zone Formation Method and System' [patent_app_type] => utility [patent_app_number] => 13/302653 [patent_app_country] => US [patent_app_date] => 2011-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3244 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13302653 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8826007 [patent_doc_number] => 20130127052 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-05-23 [patent_title] => 'Methods and Apparatus of Packaging Semiconductor Devices' [patent_app_type] => utility [patent_app_number] => 13/302551 [patent_app_country] => US [patent_app_date] => 2011-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3262 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13302551 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8615375 [patent_doc_number] => 20130020687 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-01-24 [patent_title] => 'POWER MODULE PACKAGE AND METHOD FOR MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 13/301616 [patent_app_country] => US [patent_app_date] => 2011-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4800 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13301616 [rel_patent_id] =>[rel_patent_doc_number] =>)