Search

Alexander O. Williams

Examiner (ID: 4421)

Most Active Art Unit
2826
Art Unit(s)
2508, 2826, 2811
Total Applications
2764
Issued Applications
2318
Pending Applications
64
Abandoned Applications
383

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 8275089 [patent_doc_number] => 20120168964 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-07-05 [patent_title] => 'Probe Card and Method of Testing a Semiconductor Device' [patent_app_type] => utility [patent_app_number] => 13/301222 [patent_app_country] => US [patent_app_date] => 2011-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 6035 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13301222 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/301222
Probe card including frame and cover plate for testing a semiconductor device Nov 20, 2011 Issued
Array ( [id] => 8205306 [patent_doc_number] => 20120126423 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-05-24 [patent_title] => 'SEMICONDUCTOR DEVICE MANUFACTURING METHOD AND SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 13/301154 [patent_app_country] => US [patent_app_date] => 2011-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 5486 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0126/20120126423.pdf [firstpage_image] =>[orig_patent_app_number] => 13301154 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/301154
SEMICONDUCTOR DEVICE MANUFACTURING METHOD AND SEMICONDUCTOR DEVICE Nov 20, 2011 Abandoned
Array ( [id] => 9441544 [patent_doc_number] => 08710658 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-04-29 [patent_title] => 'Under bump passive components in wafer level packaging' [patent_app_type] => utility [patent_app_number] => 13/299556 [patent_app_country] => US [patent_app_date] => 2011-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5667 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13299556 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/299556
Under bump passive components in wafer level packaging Nov 17, 2011 Issued
Array ( [id] => 8224917 [patent_doc_number] => 20120139122 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-06-07 [patent_title] => 'SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 13/298425 [patent_app_country] => US [patent_app_date] => 2011-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4964 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13298425 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/298425
Semiconductor device utilizing a package on package structure and manufacturing method thereof Nov 16, 2011 Issued
Array ( [id] => 10014557 [patent_doc_number] => 09057569 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-06-16 [patent_title] => 'Ceramic heat sink material for pressure contact structure and semiconductor module using the same' [patent_app_type] => utility [patent_app_number] => 13/988555 [patent_app_country] => US [patent_app_date] => 2011-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 10676 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13988555 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/988555
Ceramic heat sink material for pressure contact structure and semiconductor module using the same Nov 16, 2011 Issued
Array ( [id] => 8818488 [patent_doc_number] => 20130119533 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-05-16 [patent_title] => 'Package for Three Dimensional Integrated Circuit' [patent_app_type] => utility [patent_app_number] => 13/297992 [patent_app_country] => US [patent_app_date] => 2011-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 3768 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13297992 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/297992
Package for three dimensional integrated circuit Nov 15, 2011 Issued
Array ( [id] => 8818489 [patent_doc_number] => 20130119534 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-05-16 [patent_title] => 'METAL PAD STRUCTURE FOR THICKNESS ENHANCEMENT OF POLYMER USED IN ELECTRICAL INTERCONNECTION OF SEMICONDUCTOR DIE TO SEMICONDUCTOR CHIP PACKAGE SUBSTRATE WITH SOLDER BUMP' [patent_app_type] => utility [patent_app_number] => 13/298183 [patent_app_country] => US [patent_app_date] => 2011-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4285 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13298183 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/298183
Metal pad structure for thickness enhancement of polymer used in electrical interconnection of semiconductor die to semiconductor chip package substrate with solder bump Nov 15, 2011 Issued
Array ( [id] => 8818493 [patent_doc_number] => 20130119538 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-05-16 [patent_title] => 'WAFER LEVEL CHIP SIZE PACKAGE' [patent_app_type] => utility [patent_app_number] => 13/297699 [patent_app_country] => US [patent_app_date] => 2011-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2754 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13297699 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/297699
WAFER LEVEL CHIP SIZE PACKAGE Nov 15, 2011 Abandoned
Array ( [id] => 9246000 [patent_doc_number] => 08610285 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-12-17 [patent_title] => '3D IC packaging structures and methods with a metal pillar' [patent_app_type] => utility [patent_app_number] => 13/298046 [patent_app_country] => US [patent_app_date] => 2011-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2183 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13298046 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/298046
3D IC packaging structures and methods with a metal pillar Nov 15, 2011 Issued
Array ( [id] => 8818507 [patent_doc_number] => 20130119552 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-05-16 [patent_title] => 'Method for Forming Chip-on-Wafer Assembly' [patent_app_type] => utility [patent_app_number] => 13/298126 [patent_app_country] => US [patent_app_date] => 2011-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2895 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13298126 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/298126
Packages including active dies and dummy dies and methods for forming the same Nov 15, 2011 Issued
Array ( [id] => 10099890 [patent_doc_number] => 09136209 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-09-15 [patent_title] => 'Semiconductor device with specific lead frame for a power semiconductor module' [patent_app_type] => utility [patent_app_number] => 13/978456 [patent_app_country] => US [patent_app_date] => 2011-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 14 [patent_no_of_words] => 4818 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13978456 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/978456
Semiconductor device with specific lead frame for a power semiconductor module Nov 13, 2011 Issued
Array ( [id] => 9824059 [patent_doc_number] => 08933546 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-01-13 [patent_title] => 'Electronic assembly with improved thermal management' [patent_app_type] => utility [patent_app_number] => 13/978436 [patent_app_country] => US [patent_app_date] => 2011-11-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 2454 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13978436 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/978436
Electronic assembly with improved thermal management Nov 10, 2011 Issued
Array ( [id] => 9079177 [patent_doc_number] => 20130264707 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-10-10 [patent_title] => 'METHOD FOR HANDLING VERY THIN DEVICE WAFERS' [patent_app_type] => utility [patent_app_number] => 13/994660 [patent_app_country] => US [patent_app_date] => 2011-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3672 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13994660 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/994660
Structure having a planar bonding surface Sep 29, 2011 Issued
Array ( [id] => 8249187 [patent_doc_number] => 20120153511 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-06-21 [patent_title] => 'HARDMASK COMPOSITION AND METHOD OF FORMING PATTERNS AND SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE INCLUDING THE PATTERNS' [patent_app_type] => utility [patent_app_number] => 13/241479 [patent_app_country] => US [patent_app_date] => 2011-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6169 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0153/20120153511.pdf [firstpage_image] =>[orig_patent_app_number] => 13241479 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/241479
Hardmask composition including aromatic ring-containing compound, method of forming patterns, and semiconductor integrated circuit device including the patterns Sep 22, 2011 Issued
Array ( [id] => 9576038 [patent_doc_number] => 08766455 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-07-01 [patent_title] => 'Stacked semiconductor devices and fabrication methods thereof' [patent_app_type] => utility [patent_app_number] => 13/239885 [patent_app_country] => US [patent_app_date] => 2011-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 34 [patent_figures_cnt] => 36 [patent_no_of_words] => 14154 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13239885 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/239885
Stacked semiconductor devices and fabrication methods thereof Sep 21, 2011 Issued
Array ( [id] => 8193024 [patent_doc_number] => 20120119359 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-05-17 [patent_title] => 'BUMP STRUCTURE AND SEMICONDUCTOR PACKAGE HAVING THE BUMP STRUCTURE' [patent_app_type] => utility [patent_app_number] => 13/240302 [patent_app_country] => US [patent_app_date] => 2011-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 32 [patent_no_of_words] => 15334 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0119/20120119359.pdf [firstpage_image] =>[orig_patent_app_number] => 13240302 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/240302
Bump structure including nano-wires and a body connecting ends of the nano-wires, semiconductor package having the bump structure and method of manufacturing the semiconductor package Sep 21, 2011 Issued
Array ( [id] => 8730366 [patent_doc_number] => 20130075935 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-03-28 [patent_title] => 'COMPOSITE LAYERED CHIP PACKAGE' [patent_app_type] => utility [patent_app_number] => 13/240048 [patent_app_country] => US [patent_app_date] => 2011-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 53 [patent_figures_cnt] => 53 [patent_no_of_words] => 45329 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13240048 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/240048
Composite layered chip package Sep 21, 2011 Issued
Array ( [id] => 8275073 [patent_doc_number] => 20120168951 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-07-05 [patent_title] => 'PRINTED CIRCUIT BOARD AND SEMICONDUCTOR PACKAGE COMPRISING THE SAME' [patent_app_type] => utility [patent_app_number] => 13/240083 [patent_app_country] => US [patent_app_date] => 2011-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7632 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13240083 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/240083
Printed circuit board having different sub-core layers and semicondutor package comprising the same Sep 21, 2011 Issued
Array ( [id] => 8730351 [patent_doc_number] => 20130075920 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-03-28 [patent_title] => 'Multilayer Connection Structure and Making Method' [patent_app_type] => utility [patent_app_number] => 13/240058 [patent_app_country] => US [patent_app_date] => 2011-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 4293 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13240058 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/240058
Stacked IC device with recessed conductive layers adjacent to interlevel conductors Sep 21, 2011 Issued
Array ( [id] => 8730344 [patent_doc_number] => 20130075913 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-03-28 [patent_title] => 'STRUCTURE AND METHOD FOR REDUCING VERTICAL CRACK PROPAGATION' [patent_app_type] => utility [patent_app_number] => 13/239533 [patent_app_country] => US [patent_app_date] => 2011-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 3761 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13239533 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/239533
Structure and method for reducing vertical crack propagation Sep 21, 2011 Issued
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