Search

Alexander O. Williams

Examiner (ID: 4421)

Most Active Art Unit
2826
Art Unit(s)
2508, 2826, 2811
Total Applications
2764
Issued Applications
2318
Pending Applications
64
Abandoned Applications
383

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 8134097 [patent_doc_number] => 20120091597 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-04-19 [patent_title] => 'STACKED SEMICONDUCTOR PACKAGE, SEMICONDUCTOR DEVICE INCLUDING THE STACKED SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE STACKED SEMICONDUCTOR PACKAGE' [patent_app_type] => utility [patent_app_number] => 13/240515 [patent_app_country] => US [patent_app_date] => 2011-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 27 [patent_no_of_words] => 13559 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0091/20120091597.pdf [firstpage_image] =>[orig_patent_app_number] => 13240515 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/240515
Stacked semiconductor package having electrical connections or varying heights between substrates, and semiconductor device including the stacked semiconductor package Sep 21, 2011 Issued
Array ( [id] => 8910042 [patent_doc_number] => 08482109 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-07-09 [patent_title] => 'Integrated circuit packaging system with dual connection and method of manufacture thereof' [patent_app_type] => utility [patent_app_number] => 13/241141 [patent_app_country] => US [patent_app_date] => 2011-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 4752 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13241141 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/241141
Integrated circuit packaging system with dual connection and method of manufacture thereof Sep 21, 2011 Issued
Array ( [id] => 8249172 [patent_doc_number] => 20120153498 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-06-21 [patent_title] => 'Semiconductor Device and Method of Forming the Same' [patent_app_type] => utility [patent_app_number] => 13/240533 [patent_app_country] => US [patent_app_date] => 2011-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 7183 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0153/20120153498.pdf [firstpage_image] =>[orig_patent_app_number] => 13240533 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/240533
Semiconductor device and method of forming the same Sep 21, 2011 Issued
Array ( [id] => 8835078 [patent_doc_number] => 08450837 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-05-28 [patent_title] => 'Circuit device having an improved heat dissipitation, and the method of manufacturing the same' [patent_app_type] => utility [patent_app_number] => 13/240870 [patent_app_country] => US [patent_app_date] => 2011-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 18 [patent_no_of_words] => 6038 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13240870 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/240870
Circuit device having an improved heat dissipitation, and the method of manufacturing the same Sep 21, 2011 Issued
Array ( [id] => 9883268 [patent_doc_number] => 08970036 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-03-03 [patent_title] => 'Stress relieving second level interconnect structures and methods of making the same' [patent_app_type] => utility [patent_app_number] => 13/825815 [patent_app_country] => US [patent_app_date] => 2011-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 3683 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13825815 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/825815
Stress relieving second level interconnect structures and methods of making the same Sep 19, 2011 Issued
Array ( [id] => 9080505 [patent_doc_number] => 20130266035 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-10-10 [patent_title] => 'Housing and Method for Producing a Housing' [patent_app_type] => utility [patent_app_number] => 13/825290 [patent_app_country] => US [patent_app_date] => 2011-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6637 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13825290 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/825290
Housing for an optoelectronic semiconductor component and method for producing such a housing Sep 12, 2011 Issued
Array ( [id] => 8760685 [patent_doc_number] => 08421209 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-04-16 [patent_title] => 'Semiconductor device with lead terminals having portions thereof extending obliquely' [patent_app_type] => utility [patent_app_number] => 13/223364 [patent_app_country] => US [patent_app_date] => 2011-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 4122 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13223364 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/223364
Semiconductor device with lead terminals having portions thereof extending obliquely Aug 31, 2011 Issued
Array ( [id] => 8134093 [patent_doc_number] => 20120091596 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-04-19 [patent_title] => 'CHIP-TO-CHIP MULTI-SIGNALING COMMUNICATION SYSTEM WITH COMMON CONDUCTIVE LAYER' [patent_app_type] => utility [patent_app_number] => 13/210818 [patent_app_country] => US [patent_app_date] => 2011-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4246 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0091/20120091596.pdf [firstpage_image] =>[orig_patent_app_number] => 13210818 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/210818
Chip-to-chip multi-signaling communication system with common conductive layer Aug 15, 2011 Issued
Array ( [id] => 8802852 [patent_doc_number] => 08441128 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-05-14 [patent_title] => 'Semiconductor arrangement' [patent_app_type] => utility [patent_app_number] => 13/210453 [patent_app_country] => US [patent_app_date] => 2011-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 5304 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 237 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13210453 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/210453
Semiconductor arrangement Aug 15, 2011 Issued
Array ( [id] => 8669044 [patent_doc_number] => 20130043582 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-02-21 [patent_title] => 'MULTIPLE DIE IN A FACE DOWN PACKAGE' [patent_app_type] => utility [patent_app_number] => 13/209596 [patent_app_country] => US [patent_app_date] => 2011-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7094 [patent_no_of_claims] => 41 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13209596 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/209596
Multiple die in a face down package Aug 14, 2011 Issued
Array ( [id] => 8669035 [patent_doc_number] => 20130043573 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-02-21 [patent_title] => 'Solder Bump Bonding In Semiconductor Package Using Solder Balls Having High-Temperature Cores' [patent_app_type] => utility [patent_app_number] => 13/210152 [patent_app_country] => US [patent_app_date] => 2011-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6326 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13210152 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/210152
Solder Bump Bonding In Semiconductor Package Using Solder Balls Having High-Temperature Cores Aug 14, 2011 Abandoned
Array ( [id] => 8657122 [patent_doc_number] => 20130037951 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-02-14 [patent_title] => 'SEMICONDUCTOR PACKAGE STRUCTURE WITH LOW INDUCTANCE' [patent_app_type] => utility [patent_app_number] => 13/208349 [patent_app_country] => US [patent_app_date] => 2011-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2762 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13208349 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/208349
Semiconductor package structure with common gold plated metal conductor on die and substrate Aug 11, 2011 Issued
Array ( [id] => 9010010 [patent_doc_number] => 08525312 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-09-03 [patent_title] => 'Area array quad flat no-lead (QFN) package' [patent_app_type] => utility [patent_app_number] => 13/208822 [patent_app_country] => US [patent_app_date] => 2011-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 26 [patent_no_of_words] => 10438 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 218 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13208822 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/208822
Area array quad flat no-lead (QFN) package Aug 11, 2011 Issued
Array ( [id] => 9047319 [patent_doc_number] => 08541873 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-09-24 [patent_title] => 'Microelectronic packages having cavities for receiving microelectronic elements' [patent_app_type] => utility [patent_app_number] => 13/205162 [patent_app_country] => US [patent_app_date] => 2011-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 56 [patent_figures_cnt] => 125 [patent_no_of_words] => 24688 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13205162 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/205162
Microelectronic packages having cavities for receiving microelectronic elements Aug 7, 2011 Issued
Array ( [id] => 9552921 [patent_doc_number] => 08759974 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-06-24 [patent_title] => 'Solder joints with enhanced electromigration resistance' [patent_app_type] => utility [patent_app_number] => 13/205613 [patent_app_country] => US [patent_app_date] => 2011-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 1847 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 37 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13205613 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/205613
Solder joints with enhanced electromigration resistance Aug 7, 2011 Issued
Array ( [id] => 7584145 [patent_doc_number] => 20110278655 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-11-17 [patent_title] => 'Semiconductor Device with Circuit for Reduced Parasitic Inductance' [patent_app_type] => utility [patent_app_number] => 13/192584 [patent_app_country] => US [patent_app_date] => 2011-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5921 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0278/20110278655.pdf [firstpage_image] =>[orig_patent_app_number] => 13192584 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/192584
Semiconductor Device with Circuit for Reduced Parasitic Inductance Jul 27, 2011 Abandoned
Array ( [id] => 9239820 [patent_doc_number] => 08604615 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-12-10 [patent_title] => 'Semiconductor device including a stack of semiconductor chips, underfill material and molding material' [patent_app_type] => utility [patent_app_number] => 13/174813 [patent_app_country] => US [patent_app_date] => 2011-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 40 [patent_no_of_words] => 14245 [patent_no_of_claims] => 42 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 22 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13174813 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/174813
Semiconductor device including a stack of semiconductor chips, underfill material and molding material Jun 30, 2011 Issued
Array ( [id] => 8846830 [patent_doc_number] => 08456017 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-06-04 [patent_title] => 'Filled through-silicon via with conductive composite material' [patent_app_type] => utility [patent_app_number] => 13/174794 [patent_app_country] => US [patent_app_date] => 2011-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 14 [patent_no_of_words] => 3362 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13174794 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/174794
Filled through-silicon via with conductive composite material Jun 30, 2011 Issued
Array ( [id] => 9389962 [patent_doc_number] => 08686566 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-04-01 [patent_title] => 'In situ-built pin-grid arrays for coreless substrates, and methods of making same' [patent_app_type] => utility [patent_app_number] => 13/174109 [patent_app_country] => US [patent_app_date] => 2011-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 5786 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13174109 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/174109
In situ-built pin-grid arrays for coreless substrates, and methods of making same Jun 29, 2011 Issued
Array ( [id] => 9389962 [patent_doc_number] => 08686566 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-04-01 [patent_title] => 'In situ-built pin-grid arrays for coreless substrates, and methods of making same' [patent_app_type] => utility [patent_app_number] => 13/174109 [patent_app_country] => US [patent_app_date] => 2011-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 5786 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13174109 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/174109
In situ-built pin-grid arrays for coreless substrates, and methods of making same Jun 29, 2011 Issued
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