
Alexander O. Williams
Examiner (ID: 4421)
| Most Active Art Unit | 2826 |
| Art Unit(s) | 2508, 2826, 2811 |
| Total Applications | 2764 |
| Issued Applications | 2318 |
| Pending Applications | 64 |
| Abandoned Applications | 383 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 8134097
[patent_doc_number] => 20120091597
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-04-19
[patent_title] => 'STACKED SEMICONDUCTOR PACKAGE, SEMICONDUCTOR DEVICE INCLUDING THE STACKED SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE STACKED SEMICONDUCTOR PACKAGE'
[patent_app_type] => utility
[patent_app_number] => 13/240515
[patent_app_country] => US
[patent_app_date] => 2011-09-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 27
[patent_figures_cnt] => 27
[patent_no_of_words] => 13559
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[pdf_file] => publications/A1/0091/20120091597.pdf
[firstpage_image] =>[orig_patent_app_number] => 13240515
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/240515 | Stacked semiconductor package having electrical connections or varying heights between substrates, and semiconductor device including the stacked semiconductor package | Sep 21, 2011 | Issued |
Array
(
[id] => 8910042
[patent_doc_number] => 08482109
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2013-07-09
[patent_title] => 'Integrated circuit packaging system with dual connection and method of manufacture thereof'
[patent_app_type] => utility
[patent_app_number] => 13/241141
[patent_app_country] => US
[patent_app_date] => 2011-09-22
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/241141 | Integrated circuit packaging system with dual connection and method of manufacture thereof | Sep 21, 2011 | Issued |
Array
(
[id] => 8249172
[patent_doc_number] => 20120153498
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-06-21
[patent_title] => 'Semiconductor Device and Method of Forming the Same'
[patent_app_type] => utility
[patent_app_number] => 13/240533
[patent_app_country] => US
[patent_app_date] => 2011-09-22
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Array
(
[id] => 8835078
[patent_doc_number] => 08450837
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2013-05-28
[patent_title] => 'Circuit device having an improved heat dissipitation, and the method of manufacturing the same'
[patent_app_type] => utility
[patent_app_number] => 13/240870
[patent_app_country] => US
[patent_app_date] => 2011-09-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
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Array
(
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[patent_doc_number] => 08970036
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[patent_kind] => B2
[patent_issue_date] => 2015-03-03
[patent_title] => 'Stress relieving second level interconnect structures and methods of making the same'
[patent_app_type] => utility
[patent_app_number] => 13/825815
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/825815 | Stress relieving second level interconnect structures and methods of making the same | Sep 19, 2011 | Issued |
Array
(
[id] => 9080505
[patent_doc_number] => 20130266035
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-10-10
[patent_title] => 'Housing and Method for Producing a Housing'
[patent_app_type] => utility
[patent_app_number] => 13/825290
[patent_app_country] => US
[patent_app_date] => 2011-09-13
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/825290 | Housing for an optoelectronic semiconductor component and method for producing such a housing | Sep 12, 2011 | Issued |
Array
(
[id] => 8760685
[patent_doc_number] => 08421209
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2013-04-16
[patent_title] => 'Semiconductor device with lead terminals having portions thereof extending obliquely'
[patent_app_type] => utility
[patent_app_number] => 13/223364
[patent_app_country] => US
[patent_app_date] => 2011-09-01
[patent_effective_date] => 0000-00-00
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[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13223364
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/223364 | Semiconductor device with lead terminals having portions thereof extending obliquely | Aug 31, 2011 | Issued |
Array
(
[id] => 8134093
[patent_doc_number] => 20120091596
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-04-19
[patent_title] => 'CHIP-TO-CHIP MULTI-SIGNALING COMMUNICATION SYSTEM WITH COMMON CONDUCTIVE LAYER'
[patent_app_type] => utility
[patent_app_number] => 13/210818
[patent_app_country] => US
[patent_app_date] => 2011-08-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
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[pdf_file] => publications/A1/0091/20120091596.pdf
[firstpage_image] =>[orig_patent_app_number] => 13210818
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/210818 | Chip-to-chip multi-signaling communication system with common conductive layer | Aug 15, 2011 | Issued |
Array
(
[id] => 8802852
[patent_doc_number] => 08441128
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2013-05-14
[patent_title] => 'Semiconductor arrangement'
[patent_app_type] => utility
[patent_app_number] => 13/210453
[patent_app_country] => US
[patent_app_date] => 2011-08-16
[patent_effective_date] => 0000-00-00
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/210453 | Semiconductor arrangement | Aug 15, 2011 | Issued |
Array
(
[id] => 8669044
[patent_doc_number] => 20130043582
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-02-21
[patent_title] => 'MULTIPLE DIE IN A FACE DOWN PACKAGE'
[patent_app_type] => utility
[patent_app_number] => 13/209596
[patent_app_country] => US
[patent_app_date] => 2011-08-15
[patent_effective_date] => 0000-00-00
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/209596 | Multiple die in a face down package | Aug 14, 2011 | Issued |
Array
(
[id] => 8669035
[patent_doc_number] => 20130043573
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-02-21
[patent_title] => 'Solder Bump Bonding In Semiconductor Package Using Solder Balls Having High-Temperature Cores'
[patent_app_type] => utility
[patent_app_number] => 13/210152
[patent_app_country] => US
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/210152 | Solder Bump Bonding In Semiconductor Package Using Solder Balls Having High-Temperature Cores | Aug 14, 2011 | Abandoned |
Array
(
[id] => 8657122
[patent_doc_number] => 20130037951
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[patent_issue_date] => 2013-02-14
[patent_title] => 'SEMICONDUCTOR PACKAGE STRUCTURE WITH LOW INDUCTANCE'
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[patent_app_number] => 13/208349
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/208349 | Semiconductor package structure with common gold plated metal conductor on die and substrate | Aug 11, 2011 | Issued |
Array
(
[id] => 9010010
[patent_doc_number] => 08525312
[patent_country] => US
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[patent_issue_date] => 2013-09-03
[patent_title] => 'Area array quad flat no-lead (QFN) package'
[patent_app_type] => utility
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Array
(
[id] => 9047319
[patent_doc_number] => 08541873
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[patent_title] => 'Microelectronic packages having cavities for receiving microelectronic elements'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/205162 | Microelectronic packages having cavities for receiving microelectronic elements | Aug 7, 2011 | Issued |
Array
(
[id] => 9552921
[patent_doc_number] => 08759974
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[patent_kind] => B2
[patent_issue_date] => 2014-06-24
[patent_title] => 'Solder joints with enhanced electromigration resistance'
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Array
(
[id] => 7584145
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[patent_issue_date] => 2011-11-17
[patent_title] => 'Semiconductor Device with Circuit for Reduced Parasitic Inductance'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/192584 | Semiconductor Device with Circuit for Reduced Parasitic Inductance | Jul 27, 2011 | Abandoned |
Array
(
[id] => 9239820
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[patent_issue_date] => 2013-12-10
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Array
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Array
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Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/174109 | In situ-built pin-grid arrays for coreless substrates, and methods of making same | Jun 29, 2011 | Issued |