Search

Alexander O. Williams

Examiner (ID: 4421)

Most Active Art Unit
2826
Art Unit(s)
2508, 2826, 2811
Total Applications
2764
Issued Applications
2318
Pending Applications
64
Abandoned Applications
383

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6153771 [patent_doc_number] => 20110156246 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-06-30 [patent_title] => 'Semiconductor Package and Method for Making the Same' [patent_app_type] => utility [patent_app_number] => 12/796279 [patent_app_country] => US [patent_app_date] => 2010-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 4682 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0156/20110156246.pdf [firstpage_image] =>[orig_patent_app_number] => 12796279 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/796279
Semiconductor package having passive device and method for making the same Jun 7, 2010 Issued
Array ( [id] => 8283400 [patent_doc_number] => 08217502 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-07-10 [patent_title] => 'Integrated circuit packaging system with multipart conductive pillars and method of manufacture thereof' [patent_app_type] => utility [patent_app_number] => 12/796668 [patent_app_country] => US [patent_app_date] => 2010-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 16 [patent_no_of_words] => 4629 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12796668 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/796668
Integrated circuit packaging system with multipart conductive pillars and method of manufacture thereof Jun 7, 2010 Issued
Array ( [id] => 6153823 [patent_doc_number] => 20110156267 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-06-30 [patent_title] => 'Semiconductor Process, Semiconductor Element and Package Having Semiconductor Element' [patent_app_type] => utility [patent_app_number] => 12/796293 [patent_app_country] => US [patent_app_date] => 2010-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 2519 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0156/20110156267.pdf [firstpage_image] =>[orig_patent_app_number] => 12796293 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/796293
Semiconductor element and package having semiconductor element Jun 7, 2010 Issued
Array ( [id] => 8808349 [patent_doc_number] => 08446003 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-05-21 [patent_title] => 'Semiconductor device including double-sided multi-electrode chip embedded in multilayer wiring substrate' [patent_app_type] => utility [patent_app_number] => 12/785764 [patent_app_country] => US [patent_app_date] => 2010-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 24 [patent_no_of_words] => 5143 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12785764 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/785764
Semiconductor device including double-sided multi-electrode chip embedded in multilayer wiring substrate May 23, 2010 Issued
Array ( [id] => 8037267 [patent_doc_number] => 20120068359 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-03-22 [patent_title] => 'SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 13/320798 [patent_app_country] => US [patent_app_date] => 2010-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 11754 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0068/20120068359.pdf [firstpage_image] =>[orig_patent_app_number] => 13320798 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/320798
Semiconductor device manufacture in which minimum wiring pitch of connecting portion wiring layer is less than minimum wiring pitch of any other wiring layer May 17, 2010 Issued
Array ( [id] => 7763665 [patent_doc_number] => 08115318 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-02-14 [patent_title] => 'Semiconductor device having silicon-diffused metal wiring layer and its manufacturing method' [patent_app_type] => utility [patent_app_number] => 12/773493 [patent_app_country] => US [patent_app_date] => 2010-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 87 [patent_figures_cnt] => 107 [patent_no_of_words] => 14951 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/115/08115318.pdf [firstpage_image] =>[orig_patent_app_number] => 12773493 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/773493
Semiconductor device having silicon-diffused metal wiring layer and its manufacturing method May 3, 2010 Issued
Array ( [id] => 6557399 [patent_doc_number] => 20100289140 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-11-18 [patent_title] => 'SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD OF THE SEMICONDUCTOR PACKAGE' [patent_app_type] => utility [patent_app_number] => 12/760419 [patent_app_country] => US [patent_app_date] => 2010-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 11141 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0289/20100289140.pdf [firstpage_image] =>[orig_patent_app_number] => 12760419 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/760419
Semiconductor package and manufacturing method of the semiconductor package Apr 13, 2010 Issued
Array ( [id] => 8435989 [patent_doc_number] => 08283760 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-10-09 [patent_title] => 'Lead frame interconnect scheme with high power density' [patent_app_type] => utility [patent_app_number] => 12/760365 [patent_app_country] => US [patent_app_date] => 2010-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 17 [patent_no_of_words] => 3975 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12760365 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/760365
Lead frame interconnect scheme with high power density Apr 13, 2010 Issued
Array ( [id] => 8982684 [patent_doc_number] => 08513804 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-08-20 [patent_title] => 'Nanotube-based electrodes' [patent_app_type] => utility [patent_app_number] => 12/759534 [patent_app_country] => US [patent_app_date] => 2010-04-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 17 [patent_no_of_words] => 7671 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12759534 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/759534
Nanotube-based electrodes Apr 12, 2010 Issued
Array ( [id] => 4527055 [patent_doc_number] => 07952201 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-05-31 [patent_title] => 'Semiconductor device including stacked semiconductor chips' [patent_app_type] => utility [patent_app_number] => 12/759198 [patent_app_country] => US [patent_app_date] => 2010-04-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 5013 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 231 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/952/07952201.pdf [firstpage_image] =>[orig_patent_app_number] => 12759198 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/759198
Semiconductor device including stacked semiconductor chips Apr 12, 2010 Issued
Array ( [id] => 8352567 [patent_doc_number] => 08247899 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-08-21 [patent_title] => 'Power semiconductor module comprising a connection device with internal contact spring connection elements' [patent_app_type] => utility [patent_app_number] => 12/758237 [patent_app_country] => US [patent_app_date] => 2010-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 2335 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12758237 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/758237
Power semiconductor module comprising a connection device with internal contact spring connection elements Apr 11, 2010 Issued
Array ( [id] => 8215007 [patent_doc_number] => 08193648 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-06-05 [patent_title] => 'Method for detecting errors of exposed positions of a pre-layer and a current layer by an integrated alignment and overlay mark' [patent_app_type] => utility [patent_app_number] => 12/758289 [patent_app_country] => US [patent_app_date] => 2010-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3018 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 246 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/193/08193648.pdf [firstpage_image] =>[orig_patent_app_number] => 12758289 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/758289
Method for detecting errors of exposed positions of a pre-layer and a current layer by an integrated alignment and overlay mark Apr 11, 2010 Issued
12/758778 MEMORY TECHNOLOGIES Apr 11, 2010 Abandoned
Array ( [id] => 7480155 [patent_doc_number] => 20110248403 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-10-13 [patent_title] => 'Dual-Side Interconnected CMOS For Stacked Integrated Circuits' [patent_app_type] => utility [patent_app_number] => 12/758164 [patent_app_country] => US [patent_app_date] => 2010-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 3831 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0248/20110248403.pdf [firstpage_image] =>[orig_patent_app_number] => 12758164 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/758164
Dual-side interconnected CMOS for stacked integrated circuits Apr 11, 2010 Issued
Array ( [id] => 8306379 [patent_doc_number] => 08227916 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-07-24 [patent_title] => 'Package structure and method for reducing dielectric layer delamination' [patent_app_type] => utility [patent_app_number] => 12/757440 [patent_app_country] => US [patent_app_date] => 2010-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2229 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12757440 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/757440
Package structure and method for reducing dielectric layer delamination Apr 8, 2010 Issued
Array ( [id] => 6485185 [patent_doc_number] => 20100258955 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-10-14 [patent_title] => 'SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 12/757177 [patent_app_country] => US [patent_app_date] => 2010-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4486 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0258/20100258955.pdf [firstpage_image] =>[orig_patent_app_number] => 12757177 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/757177
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME Apr 8, 2010 Abandoned
Array ( [id] => 5940909 [patent_doc_number] => 20110101529 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-05-05 [patent_title] => 'BARRIER LAYER FOR COPPER INTERCONNECT' [patent_app_type] => utility [patent_app_number] => 12/757325 [patent_app_country] => US [patent_app_date] => 2010-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2953 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0101/20110101529.pdf [firstpage_image] =>[orig_patent_app_number] => 12757325 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/757325
Barrier layer for copper interconnect Apr 8, 2010 Issued
Array ( [id] => 7480157 [patent_doc_number] => 20110248404 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-10-13 [patent_title] => 'Dummy Pattern in Wafer Backside Routing' [patent_app_type] => utility [patent_app_number] => 12/756727 [patent_app_country] => US [patent_app_date] => 2010-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2525 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0248/20110248404.pdf [firstpage_image] =>[orig_patent_app_number] => 12756727 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/756727
Dummy pattern in wafer backside routing Apr 7, 2010 Issued
Array ( [id] => 6485105 [patent_doc_number] => 20100258947 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-10-14 [patent_title] => 'Nonvolatile memory devices' [patent_app_type] => utility [patent_app_number] => 12/798525 [patent_app_country] => US [patent_app_date] => 2010-04-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 5063 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0258/20100258947.pdf [firstpage_image] =>[orig_patent_app_number] => 12798525 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/798525
Nonvolatile memory devices having a three dimensional structure Apr 5, 2010 Issued
Array ( [id] => 8071665 [patent_doc_number] => 20110241192 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-10-06 [patent_title] => 'Wafer-Level Semiconductor Device Packages with Stacking Functionality' [patent_app_type] => utility [patent_app_number] => 12/753837 [patent_app_country] => US [patent_app_date] => 2010-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8421 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0241/20110241192.pdf [firstpage_image] =>[orig_patent_app_number] => 12753837 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/753837
Semiconductor device packages including connecting elements Apr 1, 2010 Issued
Menu