
Alexander O. Williams
Examiner (ID: 4421)
| Most Active Art Unit | 2826 |
| Art Unit(s) | 2508, 2826, 2811 |
| Total Applications | 2764 |
| Issued Applications | 2318 |
| Pending Applications | 64 |
| Abandoned Applications | 383 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 8386639
[patent_doc_number] => 08264038
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2012-09-11
[patent_title] => 'Buried floating layer structure for improved breakdown'
[patent_app_type] => utility
[patent_app_number] => 12/537326
[patent_app_country] => US
[patent_app_date] => 2009-08-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 15
[patent_no_of_words] => 6048
[patent_no_of_claims] => 23
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[patent_words_short_claim] => 83
[patent_maintenance] => 1
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[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12537326
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/537326 | Buried floating layer structure for improved breakdown | Aug 6, 2009 | Issued |
Array
(
[id] => 6600023
[patent_doc_number] => 20100032757
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-02-11
[patent_title] => 'BI-DIRECTIONAL DMOS WITH COMMON DRAIN'
[patent_app_type] => utility
[patent_app_number] => 12/537329
[patent_app_country] => US
[patent_app_date] => 2009-08-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
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[pdf_file] => publications/A1/0032/20100032757.pdf
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/537329 | Bi-directional DMOS with common drain | Aug 6, 2009 | Issued |
Array
(
[id] => 8153182
[patent_doc_number] => 08169076
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2012-05-01
[patent_title] => 'Interconnect structures having lead-free solder bumps'
[patent_app_type] => utility
[patent_app_number] => 12/537001
[patent_app_country] => US
[patent_app_date] => 2009-08-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
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[patent_no_of_words] => 2480
[patent_no_of_claims] => 20
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[pdf_file] => patents/08/169/08169076.pdf
[firstpage_image] =>[orig_patent_app_number] => 12537001
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/537001 | Interconnect structures having lead-free solder bumps | Aug 5, 2009 | Issued |
Array
(
[id] => 8470425
[patent_doc_number] => 08299604
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2012-10-30
[patent_title] => 'Bonded metal and ceramic plates for thermal management of optical and electronic devices'
[patent_app_type] => utility
[patent_app_number] => 12/536402
[patent_app_country] => US
[patent_app_date] => 2009-08-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
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[patent_no_of_words] => 8943
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[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12536402
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/536402 | Bonded metal and ceramic plates for thermal management of optical and electronic devices | Aug 4, 2009 | Issued |
Array
(
[id] => 5948487
[patent_doc_number] => 20110031598
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2011-02-10
[patent_title] => 'SEMICONDUCTOR DEVICE AND FABRICATING METHOD THEREOF'
[patent_app_type] => utility
[patent_app_number] => 12/535316
[patent_app_country] => US
[patent_app_date] => 2009-08-04
[patent_effective_date] => 0000-00-00
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[pdf_file] => publications/A1/0031/20110031598.pdf
[firstpage_image] =>[orig_patent_app_number] => 12535316
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/535316 | Semiconductor device having an interposer | Aug 3, 2009 | Issued |
Array
(
[id] => 5950967
[patent_doc_number] => 20110032678
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2011-02-10
[patent_title] => 'NANO-TUBE THERMAL INTERFACE STRUCTURE'
[patent_app_type] => utility
[patent_app_number] => 12/535295
[patent_app_country] => US
[patent_app_date] => 2009-08-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
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[pdf_file] => publications/A1/0032/20110032678.pdf
[firstpage_image] =>[orig_patent_app_number] => 12535295
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/535295 | Nano-tube thermal interface structure | Aug 3, 2009 | Issued |
Array
(
[id] => 6600799
[patent_doc_number] => 20100032823
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-02-11
[patent_title] => 'SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME'
[patent_app_type] => utility
[patent_app_number] => 12/534521
[patent_app_country] => US
[patent_app_date] => 2009-08-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
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[patent_no_of_words] => 3946
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[pdf_file] => publications/A1/0032/20100032823.pdf
[firstpage_image] =>[orig_patent_app_number] => 12534521
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/534521 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME | Aug 2, 2009 | Abandoned |
Array
(
[id] => 8082987
[patent_doc_number] => 08148813
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2012-04-03
[patent_title] => 'Integrated circuit package architecture'
[patent_app_type] => utility
[patent_app_number] => 12/533997
[patent_app_country] => US
[patent_app_date] => 2009-07-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 8
[patent_no_of_words] => 2910
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 2
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/08/148/08148813.pdf
[firstpage_image] =>[orig_patent_app_number] => 12533997
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/533997 | Integrated circuit package architecture | Jul 30, 2009 | Issued |
Array
(
[id] => 6247310
[patent_doc_number] => 20100025842
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-02-04
[patent_title] => 'SEMICONDUCTOR MODULE AND SEMICONDUCTOR DEVICE'
[patent_app_type] => utility
[patent_app_number] => 12/533832
[patent_app_country] => US
[patent_app_date] => 2009-07-31
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[pdf_file] => publications/A1/0025/20100025842.pdf
[firstpage_image] =>[orig_patent_app_number] => 12533832
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/533832 | SEMICONDUCTOR MODULE AND SEMICONDUCTOR DEVICE | Jul 30, 2009 | Abandoned |
Array
(
[id] => 4517869
[patent_doc_number] => 07911017
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2011-03-22
[patent_title] => 'Direct glass attached on die optical module'
[patent_app_type] => utility
[patent_app_number] => 12/459536
[patent_app_country] => US
[patent_app_date] => 2009-07-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
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[patent_no_of_words] => 5076
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/911/07911017.pdf
[firstpage_image] =>[orig_patent_app_number] => 12459536
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/459536 | Direct glass attached on die optical module | Jul 1, 2009 | Issued |
Array
(
[id] => 6591865
[patent_doc_number] => 20100001398
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-01-07
[patent_title] => 'SEMICONDUCTOR CHIP MODULE AND MANUFACTURING METHOD THEREOF'
[patent_app_type] => utility
[patent_app_number] => 12/496244
[patent_app_country] => US
[patent_app_date] => 2009-07-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
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[pdf_file] => publications/A1/0001/20100001398.pdf
[firstpage_image] =>[orig_patent_app_number] => 12496244
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/496244 | Semiconductor chip module with stacked flip-chip unit | Jun 30, 2009 | Issued |
Array
(
[id] => 5364888
[patent_doc_number] => 20090302447
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-12-10
[patent_title] => 'SEMICONDUCTOR ARRANGEMENT HAVING SPECIALLY FASHIONED BOND WIRES AND METHOD FOR FABRICATING SUCH AN ARRANGEMENT'
[patent_app_type] => utility
[patent_app_number] => 12/481255
[patent_app_country] => US
[patent_app_date] => 2009-06-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
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[pdf_file] => publications/A1/0302/20090302447.pdf
[firstpage_image] =>[orig_patent_app_number] => 12481255
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/481255 | Semiconductor arrangement having specially fashioned bond wires | Jun 8, 2009 | Issued |
Array
(
[id] => 7796377
[patent_doc_number] => 08125085
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2012-02-28
[patent_title] => 'Semiconductor device having wiring with oxide layer of impurity from the wiring'
[patent_app_type] => utility
[patent_app_number] => 12/481234
[patent_app_country] => US
[patent_app_date] => 2009-06-09
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[pdf_file] => patents/08/125/08125085.pdf
[firstpage_image] =>[orig_patent_app_number] => 12481234
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/481234 | Semiconductor device having wiring with oxide layer of impurity from the wiring | Jun 8, 2009 | Issued |
Array
(
[id] => 6400987
[patent_doc_number] => 20100148348
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-06-17
[patent_title] => 'PACKAGE SUBSTRATE'
[patent_app_type] => utility
[patent_app_number] => 12/480291
[patent_app_country] => US
[patent_app_date] => 2009-06-08
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[firstpage_image] =>[orig_patent_app_number] => 12480291
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/480291 | PACKAGE SUBSTRATE | Jun 7, 2009 | Abandoned |
Array
(
[id] => 7978611
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[patent_issue_date] => 2011-12-06
[patent_title] => 'Leadless integrated circuit package having electrically routed contacts'
[patent_app_type] => utility
[patent_app_number] => 12/479495
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/479495 | Leadless integrated circuit package having electrically routed contacts | Jun 4, 2009 | Issued |
Array
(
[id] => 7492452
[patent_doc_number] => 08030779
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[patent_kind] => B2
[patent_issue_date] => 2011-10-04
[patent_title] => 'Multi-layered metal interconnection'
[patent_app_type] => utility
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[firstpage_image] =>[orig_patent_app_number] => 12470702
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/470702 | Multi-layered metal interconnection | May 21, 2009 | Issued |
Array
(
[id] => 5567419
[patent_doc_number] => 20090250797
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-10-08
[patent_title] => ' Multi-Chip Package'
[patent_app_type] => utility
[patent_app_number] => 12/434343
[patent_app_country] => US
[patent_app_date] => 2009-05-01
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[pdf_file] => publications/A1/0250/20090250797.pdf
[firstpage_image] =>[orig_patent_app_number] => 12434343
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/434343 | Multi-chip package including die paddle with steps | Apr 30, 2009 | Issued |
Array
(
[id] => 5512108
[patent_doc_number] => 20090212412
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[patent_kind] => A1
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[patent_title] => 'SEMICONDUCTOR PACKAGE ACCOMPLISHING FAN-OUT STRUCTURE THROUGH WIRE BONDING'
[patent_app_type] => utility
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Array
(
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[patent_title] => 'MULTIPACKAGE MODULE HAVING STACKED PACKAGES WITH ASYMMETRICALLY ARRANGED DIE AND MOLDING'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/433852 | Multipackage module having stacked packages with asymmetrically arranged die and molding | Apr 29, 2009 | Issued |
Array
(
[id] => 6417490
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[patent_title] => 'SEPARATE PROBE AND BOND REGIONS OF AN INTEGRATED CIRCUIT'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/432763 | Separate probe and bond regions of an integrated circuit | Apr 29, 2009 | Issued |