
Alexander O. Williams
Examiner (ID: 17107, Phone: (571)272-1924 , Office: P/2826 )
| Most Active Art Unit | 2826 |
| Art Unit(s) | 2811, 2508, 2826 |
| Total Applications | 2764 |
| Issued Applications | 2319 |
| Pending Applications | 64 |
| Abandoned Applications | 383 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 17122462
[patent_doc_number] => 11133609
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-09-28
[patent_title] => Semiconductor device having terminal pin connected by connecting member and method of manufacturing semiconductor device
[patent_app_type] => utility
[patent_app_number] => 16/523772
[patent_app_country] => US
[patent_app_date] => 2019-07-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 14
[patent_no_of_words] => 6994
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 92
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16523772
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/523772 | Semiconductor device having terminal pin connected by connecting member and method of manufacturing semiconductor device | Jul 25, 2019 | Issued |
Array
(
[id] => 17366185
[patent_doc_number] => 11233218
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-01-25
[patent_title] => Display panel including oppositely arranging the display substrate and the packaging cover plate to form a cell and method for packaging the same, and display device
[patent_app_type] => utility
[patent_app_number] => 16/523290
[patent_app_country] => US
[patent_app_date] => 2019-07-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 12
[patent_no_of_words] => 6233
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 286
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16523290
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/523290 | Display panel including oppositely arranging the display substrate and the packaging cover plate to form a cell and method for packaging the same, and display device | Jul 25, 2019 | Issued |
Array
(
[id] => 15123429
[patent_doc_number] => 20190348348
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-11-14
[patent_title] => SEMICONDUCTOR DEVICE WITH LEAD TERMINALS HAVING PORTIONS THEREOF EXTENDING OBLIQUELY
[patent_app_type] => utility
[patent_app_number] => 16/519591
[patent_app_country] => US
[patent_app_date] => 2019-07-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4971
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 147
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16519591
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/519591 | Semiconductor device with lead terminals having portions thereof extending obliquely | Jul 22, 2019 | Issued |
Array
(
[id] => 16432883
[patent_doc_number] => 10832980
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-11-10
[patent_title] => Electronic component housing package, multi-piece wiring substrate, electronic apparatus, and electronic module
[patent_app_type] => utility
[patent_app_number] => 16/509163
[patent_app_country] => US
[patent_app_date] => 2019-07-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 6
[patent_no_of_words] => 8940
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 221
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16509163
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/509163 | Electronic component housing package, multi-piece wiring substrate, electronic apparatus, and electronic module | Jul 10, 2019 | Issued |
Array
(
[id] => 14904287
[patent_doc_number] => 20190295909
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-09-26
[patent_title] => PACKAGE SUBSTRATE FOR SEMICONDUCTOR PACKAGE, SEMICONDUCTOR PACKAGE INCLUDING THE SAME AND METHOD OF MANUFACTURING THE SAME
[patent_app_type] => utility
[patent_app_number] => 16/441591
[patent_app_country] => US
[patent_app_date] => 2019-06-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6211
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 103
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16441591
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/441591 | Package substrate for a semiconductor package having landing pads extending toward a through-hole in a chip mounting region | Jun 13, 2019 | Issued |
Array
(
[id] => 16699978
[patent_doc_number] => 10950586
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-03-16
[patent_title] => Semiconductor devices having upper and lower solder portions and methods of fabricating the same
[patent_app_type] => utility
[patent_app_number] => 16/437595
[patent_app_country] => US
[patent_app_date] => 2019-06-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 10
[patent_no_of_words] => 3974
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 173
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16437595
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/437595 | Semiconductor devices having upper and lower solder portions and methods of fabricating the same | Jun 10, 2019 | Issued |
Array
(
[id] => 16845997
[patent_doc_number] => 11018093
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-05-25
[patent_title] => Magnetic shielding of STT-MRAM in multichip packaging and method of manufacturing the same
[patent_app_type] => utility
[patent_app_number] => 16/432500
[patent_app_country] => US
[patent_app_date] => 2019-06-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 12
[patent_no_of_words] => 2668
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 55
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16432500
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/432500 | Magnetic shielding of STT-MRAM in multichip packaging and method of manufacturing the same | Jun 4, 2019 | Issued |
Array
(
[id] => 15984683
[patent_doc_number] => 10672678
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-06-02
[patent_title] => Method for forming a chip package with compounds to improve the durability and performance of metal contact structures in the chip package
[patent_app_type] => utility
[patent_app_number] => 16/431808
[patent_app_country] => US
[patent_app_date] => 2019-06-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 8
[patent_no_of_words] => 11181
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 196
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16431808
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/431808 | Method for forming a chip package with compounds to improve the durability and performance of metal contact structures in the chip package | Jun 4, 2019 | Issued |
Array
(
[id] => 14842963
[patent_doc_number] => 20190279882
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-09-12
[patent_title] => ELECTRONIC DEVICE WITH TOP SIDE PIN ARRAY AND MANUFACTURING METHOD THEREOF
[patent_app_type] => utility
[patent_app_number] => 16/424046
[patent_app_country] => US
[patent_app_date] => 2019-05-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 11382
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 91
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16424046
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/424046 | Electronic device with top side pin array and manufacturing method thereof | May 27, 2019 | Issued |
Array
(
[id] => 15332215
[patent_doc_number] => 20200006437
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-01-02
[patent_title] => DISPLAY DEVICE
[patent_app_type] => utility
[patent_app_number] => 16/415263
[patent_app_country] => US
[patent_app_date] => 2019-05-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10165
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 87
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16415263
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/415263 | Display device comprising buffer layer and encapsulation layer | May 16, 2019 | Issued |
Array
(
[id] => 16789367
[patent_doc_number] => 10991806
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-04-27
[patent_title] => Two-transistor memory device and method for fabricating memory device
[patent_app_type] => utility
[patent_app_number] => 16/408214
[patent_app_country] => US
[patent_app_date] => 2019-05-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 14
[patent_no_of_words] => 4407
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 115
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16408214
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/408214 | Two-transistor memory device and method for fabricating memory device | May 8, 2019 | Issued |
Array
(
[id] => 17329970
[patent_doc_number] => 11220423
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-01-11
[patent_title] => Reduced MEMS cavity gap
[patent_app_type] => utility
[patent_app_number] => 16/408239
[patent_app_country] => US
[patent_app_date] => 2019-05-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 7
[patent_no_of_words] => 2768
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 72
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16408239
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/408239 | Reduced MEMS cavity gap | May 8, 2019 | Issued |
Array
(
[id] => 15969627
[patent_doc_number] => 20200168565
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-05-28
[patent_title] => SEMICONDUCTOR PACKAGE
[patent_app_type] => utility
[patent_app_number] => 16/406951
[patent_app_country] => US
[patent_app_date] => 2019-05-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9616
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 81
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16406951
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/406951 | Semiconductor package | May 7, 2019 | Issued |
Array
(
[id] => 14784711
[patent_doc_number] => 20190267253
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-08-29
[patent_title] => ADHESIVE-BONDED THERMAL INTERFACE STRUCTURES
[patent_app_type] => utility
[patent_app_number] => 16/405578
[patent_app_country] => US
[patent_app_date] => 2019-05-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 14629
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -13
[patent_words_short_claim] => 94
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16405578
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/405578 | Adhesive-bonded thermal interface structures | May 6, 2019 | Issued |
Array
(
[id] => 14784713
[patent_doc_number] => 20190267254
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-08-29
[patent_title] => ADHESIVE-BONDED THERMAL INTERFACE STRUCTURES
[patent_app_type] => utility
[patent_app_number] => 16/405614
[patent_app_country] => US
[patent_app_date] => 2019-05-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 14629
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -19
[patent_words_short_claim] => 123
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16405614
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/405614 | ADHESIVE-BONDED THERMAL INTERFACE STRUCTURES | May 6, 2019 | Abandoned |
Array
(
[id] => 14753357
[patent_doc_number] => 20190259852
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-08-22
[patent_title] => FINFET WITH REDUCED PARASITIC CAPACITANCE
[patent_app_type] => utility
[patent_app_number] => 16/402264
[patent_app_country] => US
[patent_app_date] => 2019-05-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7284
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -12
[patent_words_short_claim] => 96
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16402264
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/402264 | FINFET WITH REDUCED PARASITIC CAPACITANCE | May 2, 2019 | Abandoned |
Array
(
[id] => 16202031
[patent_doc_number] => 10727211
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-07-28
[patent_title] => Package structure with dummy die
[patent_app_type] => utility
[patent_app_number] => 16/396053
[patent_app_country] => US
[patent_app_date] => 2019-04-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 29
[patent_no_of_words] => 6785
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 84
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16396053
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/396053 | Package structure with dummy die | Apr 25, 2019 | Issued |
Array
(
[id] => 16402303
[patent_doc_number] => 20200343161
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-10-29
[patent_title] => POROUS BARRIER LAYER FOR IMPROVING RELIABILITY OF THROUGH-SUBSTRATE VIA STRUCTURES AND METHODS OF FORMING THE SAME
[patent_app_type] => utility
[patent_app_number] => 16/391632
[patent_app_country] => US
[patent_app_date] => 2019-04-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9396
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 184
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16391632
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/391632 | Porous barrier layer for improving reliability of through-substrate via structures and methods of forming the same | Apr 22, 2019 | Issued |
Array
(
[id] => 15093157
[patent_doc_number] => 20190341390
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-11-07
[patent_title] => Non-Volatile Memory Device and Manufacturing Method
[patent_app_type] => utility
[patent_app_number] => 16/391768
[patent_app_country] => US
[patent_app_date] => 2019-04-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6825
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -19
[patent_words_short_claim] => 67
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16391768
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/391768 | Non-volatile memory device with vertical state transistor and vertical selection transistor | Apr 22, 2019 | Issued |
Array
(
[id] => 14691613
[patent_doc_number] => 20190244922
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-08-08
[patent_title] => NICKEL-TIN MICROBUMP STRUCTURES AND METHOD OF MAKING SAME
[patent_app_type] => utility
[patent_app_number] => 16/386195
[patent_app_country] => US
[patent_app_date] => 2019-04-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6213
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 68
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16386195
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/386195 | NICKEL-TIN MICROBUMP STRUCTURES AND METHOD OF MAKING SAME | Apr 15, 2019 | Abandoned |