
Alexander O. Williams
Examiner (ID: 4421)
| Most Active Art Unit | 2826 |
| Art Unit(s) | 2508, 2826, 2811 |
| Total Applications | 2764 |
| Issued Applications | 2318 |
| Pending Applications | 64 |
| Abandoned Applications | 383 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 4433605
[patent_doc_number] => 07969018
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-06-28
[patent_title] => 'Stacked semiconductor chips with separate encapsulations'
[patent_app_type] => utility
[patent_app_number] => 12/173444
[patent_app_country] => US
[patent_app_date] => 2008-07-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 36
[patent_no_of_words] => 6903
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 118
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/969/07969018.pdf
[firstpage_image] =>[orig_patent_app_number] => 12173444
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/173444 | Stacked semiconductor chips with separate encapsulations | Jul 14, 2008 | Issued |
Array
(
[id] => 6280710
[patent_doc_number] => 20100155967
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-06-24
[patent_title] => 'INTEGRATED CIRCUITS ON A WAFER AND METHOD OF PRODUCING INTEGRATED CIRCUITS'
[patent_app_type] => utility
[patent_app_number] => 12/668488
[patent_app_country] => US
[patent_app_date] => 2008-07-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 3483
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0155/20100155967.pdf
[firstpage_image] =>[orig_patent_app_number] => 12668488
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/668488 | Integrated circuits on a wafer and method of producing integrated circuits | Jul 9, 2008 | Issued |
Array
(
[id] => 4958733
[patent_doc_number] => 20080273157
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-11-06
[patent_title] => 'Display device having misalignment detection pattern for detecting misalignment between conductive layer and insulating layer'
[patent_app_type] => utility
[patent_app_number] => 12/216541
[patent_app_country] => US
[patent_app_date] => 2008-07-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 4529
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0273/20080273157.pdf
[firstpage_image] =>[orig_patent_app_number] => 12216541
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/216541 | Display device having misalignment detection pattern for detecting misalignment between conductive layer and insulating layer | Jul 6, 2008 | Abandoned |
Array
(
[id] => 5295517
[patent_doc_number] => 20090010443
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-01-08
[patent_title] => 'Method and Device for Determining a Room Acoustic Impulse Response in the Time Domain'
[patent_app_type] => utility
[patent_app_number] => 12/168112
[patent_app_country] => US
[patent_app_date] => 2008-07-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 14
[patent_no_of_words] => 6743
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0010/20090010443.pdf
[firstpage_image] =>[orig_patent_app_number] => 12168112
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/168112 | Method and device for determining a room acoustic impulse response in the time domain | Jul 4, 2008 | Issued |
Array
(
[id] => 4564420
[patent_doc_number] => 07838974
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-11-23
[patent_title] => 'Intergrated circuit packaging with improved die bonding'
[patent_app_type] => utility
[patent_app_number] => 12/167163
[patent_app_country] => US
[patent_app_date] => 2008-07-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 19
[patent_no_of_words] => 6062
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 225
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/838/07838974.pdf
[firstpage_image] =>[orig_patent_app_number] => 12167163
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/167163 | Intergrated circuit packaging with improved die bonding | Jul 1, 2008 | Issued |
Array
(
[id] => 4433459
[patent_doc_number] => 07968979
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-06-28
[patent_title] => 'Integrated circuit package system with conformal shielding and method of manufacture thereof'
[patent_app_type] => utility
[patent_app_number] => 12/146124
[patent_app_country] => US
[patent_app_date] => 2008-06-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 19
[patent_no_of_words] => 6889
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 92
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/968/07968979.pdf
[firstpage_image] =>[orig_patent_app_number] => 12146124
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/146124 | Integrated circuit package system with conformal shielding and method of manufacture thereof | Jun 24, 2008 | Issued |
Array
(
[id] => 6272266
[patent_doc_number] => 20100117232
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-05-13
[patent_title] => 'SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME'
[patent_app_type] => utility
[patent_app_number] => 12/452235
[patent_app_country] => US
[patent_app_date] => 2008-06-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 14
[patent_no_of_words] => 10145
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0117/20100117232.pdf
[firstpage_image] =>[orig_patent_app_number] => 12452235
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/452235 | Semiconductor device having an electrode and method for manufacturing the same | Jun 19, 2008 | Issued |
Array
(
[id] => 5288163
[patent_doc_number] => 20090020893
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-01-22
[patent_title] => 'INTEGRATED CIRCUIT PACKAGE SYSTEM WITH TRIPLE FILM SPACER'
[patent_app_type] => utility
[patent_app_number] => 12/142743
[patent_app_country] => US
[patent_app_date] => 2008-06-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 3444
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0020/20090020893.pdf
[firstpage_image] =>[orig_patent_app_number] => 12142743
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/142743 | Integrated circuit package system with triple film spacer having embedded fillers and method of manufacture thereof | Jun 18, 2008 | Issued |
Array
(
[id] => 4756710
[patent_doc_number] => 20080308935
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-12-18
[patent_title] => 'SEMICONDUCTOR CHIP PACKAGE, SEMICONDUCTOR PACKAGE INCLUDING SEMICONDUCTOR CHIP PACKAGE, AND METHOD OF FABRICATING SEMICONDUCTOR PACKAGE'
[patent_app_type] => utility
[patent_app_number] => 12/141764
[patent_app_country] => US
[patent_app_date] => 2008-06-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 9788
[patent_no_of_claims] => 54
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0308/20080308935.pdf
[firstpage_image] =>[orig_patent_app_number] => 12141764
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/141764 | SEMICONDUCTOR CHIP PACKAGE, SEMICONDUCTOR PACKAGE INCLUDING SEMICONDUCTOR CHIP PACKAGE, AND METHOD OF FABRICATING SEMICONDUCTOR PACKAGE | Jun 17, 2008 | Abandoned |
Array
(
[id] => 7775672
[patent_doc_number] => 08120189
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2012-02-21
[patent_title] => 'Wiring terminal-connecting adhesive'
[patent_app_type] => utility
[patent_app_number] => 12/139306
[patent_app_country] => US
[patent_app_date] => 2008-06-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 7377
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 44
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/08/120/08120189.pdf
[firstpage_image] =>[orig_patent_app_number] => 12139306
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/139306 | Wiring terminal-connecting adhesive | Jun 12, 2008 | Issued |
Array
(
[id] => 4660881
[patent_doc_number] => 20080251788
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-10-16
[patent_title] => 'Wafer-level package having test terminal'
[patent_app_type] => utility
[patent_app_number] => 12/155783
[patent_app_country] => US
[patent_app_date] => 2008-06-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 13
[patent_no_of_words] => 10396
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0251/20080251788.pdf
[firstpage_image] =>[orig_patent_app_number] => 12155783
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/155783 | Wafer-level package having test terminal | Jun 9, 2008 | Issued |
Array
(
[id] => 5543
[patent_doc_number] => 07812431
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-10-12
[patent_title] => 'Leadframe with die pad and leads corresponding thereto'
[patent_app_type] => utility
[patent_app_number] => 12/133443
[patent_app_country] => US
[patent_app_date] => 2008-06-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 3
[patent_no_of_words] => 1227
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 119
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/812/07812431.pdf
[firstpage_image] =>[orig_patent_app_number] => 12133443
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/133443 | Leadframe with die pad and leads corresponding thereto | Jun 4, 2008 | Issued |
Array
(
[id] => 8082973
[patent_doc_number] => 08148808
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2012-04-03
[patent_title] => 'Partitioning of electronic packages'
[patent_app_type] => utility
[patent_app_number] => 12/156673
[patent_app_country] => US
[patent_app_date] => 2008-06-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 14
[patent_no_of_words] => 3537
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 158
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/08/148/08148808.pdf
[firstpage_image] =>[orig_patent_app_number] => 12156673
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/156673 | Partitioning of electronic packages | Jun 1, 2008 | Issued |
Array
(
[id] => 4789543
[patent_doc_number] => 20080290516
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-11-27
[patent_title] => 'SEMICONDUCTOR DEVICE WITH BONDING PAD SUPPORT STRUCTURE'
[patent_app_type] => utility
[patent_app_number] => 12/129180
[patent_app_country] => US
[patent_app_date] => 2008-05-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 7817
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
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[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0290/20080290516.pdf
[firstpage_image] =>[orig_patent_app_number] => 12129180
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/129180 | SEMICONDUCTOR DEVICE WITH BONDING PAD SUPPORT STRUCTURE | May 28, 2008 | Abandoned |
Array
(
[id] => 5300342
[patent_doc_number] => 20090294994
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-12-03
[patent_title] => 'BOND PAD STRUCTURE'
[patent_app_type] => utility
[patent_app_number] => 12/129333
[patent_app_country] => US
[patent_app_date] => 2008-05-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 4939
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0294/20090294994.pdf
[firstpage_image] =>[orig_patent_app_number] => 12129333
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/129333 | Bond pad structure located over active circuit structure | May 28, 2008 | Issued |
Array
(
[id] => 5275551
[patent_doc_number] => 20090127683
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-05-21
[patent_title] => 'INTEGRATED CIRCUIT PACKAGE SYSTEM WITH INSULATOR'
[patent_app_type] => utility
[patent_app_number] => 12/126684
[patent_app_country] => US
[patent_app_date] => 2008-05-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 4350
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0127/20090127683.pdf
[firstpage_image] =>[orig_patent_app_number] => 12126684
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/126684 | Integrated circuit package system with insulator over circuitry | May 22, 2008 | Issued |
Array
(
[id] => 4836938
[patent_doc_number] => 20080277802
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-11-13
[patent_title] => 'Flip-chip semiconductor package and package substrate applicable thereto'
[patent_app_type] => utility
[patent_app_number] => 12/151904
[patent_app_country] => US
[patent_app_date] => 2008-05-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 2548
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0277/20080277802.pdf
[firstpage_image] =>[orig_patent_app_number] => 12151904
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/151904 | Flip-chip semiconductor package and package substrate applicable thereto | May 7, 2008 | Abandoned |
Array
(
[id] => 4870743
[patent_doc_number] => 20080197477
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-08-21
[patent_title] => 'Flip-Chip Grid Ball Array Strip and Package'
[patent_app_type] => utility
[patent_app_number] => 12/110798
[patent_app_country] => US
[patent_app_date] => 2008-04-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 5528
[patent_no_of_claims] => 25
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0197/20080197477.pdf
[firstpage_image] =>[orig_patent_app_number] => 12110798
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/110798 | Integrated package circuit with stiffener | Apr 27, 2008 | Issued |
Array
(
[id] => 7492429
[patent_doc_number] => 08030768
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-10-04
[patent_title] => 'Semiconductor package with under bump metallization aligned with open vias'
[patent_app_type] => utility
[patent_app_number] => 12/108563
[patent_app_country] => US
[patent_app_date] => 2008-04-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/08/030/08030768.pdf
[firstpage_image] =>[orig_patent_app_number] => 12108563
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/108563 | Semiconductor package with under bump metallization aligned with open vias | Apr 23, 2008 | Issued |
Array
(
[id] => 4737262
[patent_doc_number] => 20080230914
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-09-25
[patent_title] => 'SEMICONDUCTOR ELEMENT, METHOD OF MANUFACTURING SEMICONDUCTOR ELEMENT, MULTI-LAYER PRINTED CIRCUIT BOARD, AND METHOD OF MANUFACTURING MULTI-LAYER PRINTED CIRCUIT BOARD'
[patent_app_type] => utility
[patent_app_number] => 12/107364
[patent_app_country] => US
[patent_app_date] => 2008-04-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 71
[patent_figures_cnt] => 71
[patent_no_of_words] => 33556
[patent_no_of_claims] => 26
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0230/20080230914.pdf
[firstpage_image] =>[orig_patent_app_number] => 12107364
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/107364 | Semiconductor element connected to printed circuit board | Apr 21, 2008 | Issued |