Search

Alexander O. Williams

Examiner (ID: 4421)

Most Active Art Unit
2826
Art Unit(s)
2508, 2826, 2811
Total Applications
2764
Issued Applications
2318
Pending Applications
64
Abandoned Applications
383

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 93052 [patent_doc_number] => 07737513 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-06-15 [patent_title] => 'Chip assembly including package element and integrated circuit chip' [patent_app_type] => utility [patent_app_number] => 11/809213 [patent_app_country] => US [patent_app_date] => 2007-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 4197 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/737/07737513.pdf [firstpage_image] =>[orig_patent_app_number] => 11809213 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/809213
Chip assembly including package element and integrated circuit chip May 29, 2007 Issued
Array ( [id] => 4708222 [patent_doc_number] => 20080296748 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-12-04 [patent_title] => 'Transmission line stacking' [patent_app_type] => utility [patent_app_number] => 11/809214 [patent_app_country] => US [patent_app_date] => 2007-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 5239 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0296/20080296748.pdf [firstpage_image] =>[orig_patent_app_number] => 11809214 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/809214
Microelectronic package having interconnected redistribution paths May 29, 2007 Issued
Array ( [id] => 142678 [patent_doc_number] => 07687885 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-03-30 [patent_title] => 'Semiconductor device with reduced parasitic inductance' [patent_app_type] => utility [patent_app_number] => 11/809023 [patent_app_country] => US [patent_app_date] => 2007-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 18 [patent_no_of_words] => 5883 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 340 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/687/07687885.pdf [firstpage_image] =>[orig_patent_app_number] => 11809023 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/809023
Semiconductor device with reduced parasitic inductance May 29, 2007 Issued
Array ( [id] => 43701 [patent_doc_number] => 07781898 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-08-24 [patent_title] => 'IC package reducing wiring layers on substrate and its chip carrier' [patent_app_type] => utility [patent_app_number] => 11/806023 [patent_app_country] => US [patent_app_date] => 2007-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 2264 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/781/07781898.pdf [firstpage_image] =>[orig_patent_app_number] => 11806023 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/806023
IC package reducing wiring layers on substrate and its chip carrier May 28, 2007 Issued
Array ( [id] => 5008159 [patent_doc_number] => 20070278636 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-12-06 [patent_title] => 'Matching Circuits On Optoelectronic Devices' [patent_app_type] => utility [patent_app_number] => 11/753270 [patent_app_country] => US [patent_app_date] => 2007-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2178 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0278/20070278636.pdf [firstpage_image] =>[orig_patent_app_number] => 11753270 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/753270
Matching circuits on optoelectronic devices May 23, 2007 Issued
Array ( [id] => 5256803 [patent_doc_number] => 20070210435 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-09-13 [patent_title] => 'STACKED MICROELECTRONIC DIES AND METHODS FOR STACKING MICROELECTRONIC DIES' [patent_app_type] => utility [patent_app_number] => 11/751402 [patent_app_country] => US [patent_app_date] => 2007-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3384 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0210/20070210435.pdf [firstpage_image] =>[orig_patent_app_number] => 11751402 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/751402
Stacked microelectronic device assemblies May 20, 2007 Issued
Array ( [id] => 260406 [patent_doc_number] => 07573135 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-08-11 [patent_title] => 'Electronic parts packaging structure in which a semiconductor chip is mounted on a wiring substrate and buried in an insulation film' [patent_app_type] => utility [patent_app_number] => 11/798813 [patent_app_country] => US [patent_app_date] => 2007-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 33 [patent_no_of_words] => 10072 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 229 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/573/07573135.pdf [firstpage_image] =>[orig_patent_app_number] => 11798813 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/798813
Electronic parts packaging structure in which a semiconductor chip is mounted on a wiring substrate and buried in an insulation film May 16, 2007 Issued
Array ( [id] => 4776012 [patent_doc_number] => 20080284010 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-11-20 [patent_title] => 'Apparatus for connecting integrated circuit chip to power and ground circuits' [patent_app_type] => utility [patent_app_number] => 11/804003 [patent_app_country] => US [patent_app_date] => 2007-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5493 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0284/20080284010.pdf [firstpage_image] =>[orig_patent_app_number] => 11804003 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/804003
Apparatus for connecting integrated circuit chip to power and ground circuits May 15, 2007 Issued
Array ( [id] => 4472452 [patent_doc_number] => 07944035 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-05-17 [patent_title] => 'Double sided semiconduction device with edge contact and package therefor' [patent_app_type] => utility [patent_app_number] => 11/803763 [patent_app_country] => US [patent_app_date] => 2007-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 24 [patent_no_of_words] => 2300 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/944/07944035.pdf [firstpage_image] =>[orig_patent_app_number] => 11803763 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/803763
Double sided semiconduction device with edge contact and package therefor May 15, 2007 Issued
Array ( [id] => 5256808 [patent_doc_number] => 20070210440 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-09-13 [patent_title] => 'Semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/801702 [patent_app_country] => US [patent_app_date] => 2007-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 10473 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0210/20070210440.pdf [firstpage_image] =>[orig_patent_app_number] => 11801702 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/801702
Semiconductor device May 9, 2007 Abandoned
Array ( [id] => 5026286 [patent_doc_number] => 20070267732 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-11-22 [patent_title] => 'Circuit card module and method for fabricating the same' [patent_app_type] => utility [patent_app_number] => 11/801303 [patent_app_country] => US [patent_app_date] => 2007-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5287 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0267/20070267732.pdf [firstpage_image] =>[orig_patent_app_number] => 11801303 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/801303
Circuit card module and method for fabricating the same May 7, 2007 Abandoned
Array ( [id] => 4876780 [patent_doc_number] => 20080150163 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-06-26 [patent_title] => 'Mounting structure for semiconductor element' [patent_app_type] => utility [patent_app_number] => 11/797883 [patent_app_country] => US [patent_app_date] => 2007-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 5021 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0150/20080150163.pdf [firstpage_image] =>[orig_patent_app_number] => 11797883 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/797883
Mounting structure for semiconductor element May 7, 2007 Issued
Array ( [id] => 274647 [patent_doc_number] => 07560814 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-07-14 [patent_title] => 'Semiconductor device that improves electrical connection reliability' [patent_app_type] => utility [patent_app_number] => 11/797476 [patent_app_country] => US [patent_app_date] => 2007-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 3875 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 274 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/560/07560814.pdf [firstpage_image] =>[orig_patent_app_number] => 11797476 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/797476
Semiconductor device that improves electrical connection reliability May 2, 2007 Issued
Array ( [id] => 4958061 [patent_doc_number] => 20080272485 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-11-06 [patent_title] => 'Liquid cooled power electronic circuit comprising stacked direct die cooled packages' [patent_app_type] => utility [patent_app_number] => 11/800003 [patent_app_country] => US [patent_app_date] => 2007-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4364 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0272/20080272485.pdf [firstpage_image] =>[orig_patent_app_number] => 11800003 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/800003
Liquid cooled power electronic circuit comprising stacked direct die cooled packages May 2, 2007 Issued
Array ( [id] => 5208228 [patent_doc_number] => 20070246812 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-10-25 [patent_title] => 'High reliability power module' [patent_app_type] => utility [patent_app_number] => 11/789164 [patent_app_country] => US [patent_app_date] => 2007-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3399 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0246/20070246812.pdf [firstpage_image] =>[orig_patent_app_number] => 11789164 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/789164
High reliability power module Apr 23, 2007 Issued
Array ( [id] => 296396 [patent_doc_number] => 07541669 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-06-02 [patent_title] => 'Semiconductor device package with base features to reduce leakage' [patent_app_type] => utility [patent_app_number] => 11/788346 [patent_app_country] => US [patent_app_date] => 2007-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 8 [patent_no_of_words] => 2838 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/541/07541669.pdf [firstpage_image] =>[orig_patent_app_number] => 11788346 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/788346
Semiconductor device package with base features to reduce leakage Apr 18, 2007 Issued
Array ( [id] => 300213 [patent_doc_number] => 07538417 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-05-26 [patent_title] => 'Semiconductor device with signal line having decreased characteristic impedance' [patent_app_type] => utility [patent_app_number] => 11/785708 [patent_app_country] => US [patent_app_date] => 2007-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 27 [patent_no_of_words] => 7360 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 244 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/538/07538417.pdf [firstpage_image] =>[orig_patent_app_number] => 11785708 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/785708
Semiconductor device with signal line having decreased characteristic impedance Apr 18, 2007 Issued
Array ( [id] => 4749292 [patent_doc_number] => 20080157363 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-07-03 [patent_title] => 'Method of forming the nanoscale conductive structure and a semiconductor device formed thereby' [patent_app_type] => utility [patent_app_number] => 11/785164 [patent_app_country] => US [patent_app_date] => 2007-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3528 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0157/20080157363.pdf [firstpage_image] =>[orig_patent_app_number] => 11785164 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/785164
Semiconductor device having a nanoscale conductive structure Apr 15, 2007 Issued
Array ( [id] => 570948 [patent_doc_number] => 07466016 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-12-16 [patent_title] => 'Bent lead transistor' [patent_app_type] => utility [patent_app_number] => 11/784763 [patent_app_country] => US [patent_app_date] => 2007-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 7 [patent_no_of_words] => 1847 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 235 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/466/07466016.pdf [firstpage_image] =>[orig_patent_app_number] => 11784763 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/784763
Bent lead transistor Apr 6, 2007 Issued
Array ( [id] => 63678 [patent_doc_number] => 07763973 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-07-27 [patent_title] => 'Integrated heat sink for a microchip' [patent_app_type] => utility [patent_app_number] => 11/784463 [patent_app_country] => US [patent_app_date] => 2007-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 3127 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/763/07763973.pdf [firstpage_image] =>[orig_patent_app_number] => 11784463 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/784463
Integrated heat sink for a microchip Apr 4, 2007 Issued
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