Search

Alexander P. Taousakis

Examiner (ID: 144)

Most Active Art Unit
3726
Art Unit(s)
3726
Total Applications
799
Issued Applications
568
Pending Applications
0
Abandoned Applications
233

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1478221 [patent_doc_number] => 06451704 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-17 [patent_title] => 'Method for forming PLDD structure with minimized lateral dopant diffusion' [patent_app_type] => B1 [patent_app_number] => 09/849672 [patent_app_country] => US [patent_app_date] => 2001-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 5787 [patent_no_of_claims] => 44 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 333 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/451/06451704.pdf [firstpage_image] =>[orig_patent_app_number] => 09849672 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/849672
Method for forming PLDD structure with minimized lateral dopant diffusion May 6, 2001 Issued
09/831284 Method for fabricating printed substrate, method for fabricating recording apparatus and mask for use in fabrication of printed substrate May 3, 2001 Abandoned
Array ( [id] => 6095954 [patent_doc_number] => 20020052118 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-05-02 [patent_title] => 'Method for forming isolation regions on semiconductor device' [patent_app_type] => new [patent_app_number] => 09/847274 [patent_app_country] => US [patent_app_date] => 2001-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5329 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0052/20020052118.pdf [firstpage_image] =>[orig_patent_app_number] => 09847274 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/847274
Method for forming isolation regions on semiconductor device May 2, 2001 Issued
Array ( [id] => 7012301 [patent_doc_number] => 20010050266 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-12-13 [patent_title] => 'Single mask technique for making positive and negative micromachined features on a substrate' [patent_app_type] => new [patent_app_number] => 09/847798 [patent_app_country] => US [patent_app_date] => 2001-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 5887 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0050/20010050266.pdf [firstpage_image] =>[orig_patent_app_number] => 09847798 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/847798
Single mask technique for making positive and negative micromachined features on a substrate May 1, 2001 Issued
Array ( [id] => 6889421 [patent_doc_number] => 20010024876 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-09-27 [patent_title] => 'Fabrication process of semiconductor substrate' [patent_app_type] => new [patent_app_number] => 09/840895 [patent_app_country] => US [patent_app_date] => 2001-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 22832 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0024/20010024876.pdf [firstpage_image] =>[orig_patent_app_number] => 09840895 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/840895
Fabrication process of semiconductor substrate Apr 24, 2001 Issued
Array ( [id] => 7028265 [patent_doc_number] => 20010014536 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-08-16 [patent_title] => 'Substrate processing method and apparatus' [patent_app_type] => new [patent_app_number] => 09/840111 [patent_app_country] => US [patent_app_date] => 2001-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 10458 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0014/20010014536.pdf [firstpage_image] =>[orig_patent_app_number] => 09840111 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/840111
Substrate processing method and apparatus Apr 23, 2001 Abandoned
Array ( [id] => 6617897 [patent_doc_number] => 20020016080 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-02-07 [patent_title] => 'Two etchant etch method' [patent_app_type] => new [patent_app_number] => 09/836934 [patent_app_country] => US [patent_app_date] => 2001-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 15480 [patent_no_of_claims] => 60 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0016/20020016080.pdf [firstpage_image] =>[orig_patent_app_number] => 09836934 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/836934
Two etchant etch method Apr 16, 2001 Issued
Array ( [id] => 6540395 [patent_doc_number] => 20020137355 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-09-26 [patent_title] => 'PROCESS FOR FORMING UNIFORM MULTIPLE CONTACT HOLES' [patent_app_type] => new [patent_app_number] => 09/828610 [patent_app_country] => US [patent_app_date] => 2001-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2000 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 291 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0137/20020137355.pdf [firstpage_image] =>[orig_patent_app_number] => 09828610 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/828610
Process for forming uniform multiple contact holes Apr 8, 2001 Issued
Array ( [id] => 6881506 [patent_doc_number] => 20010047978 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-12-06 [patent_title] => 'Process for the double-side polishing of semiconductor wafers and carrier for carrying out the process' [patent_app_type] => new [patent_app_number] => 09/826135 [patent_app_country] => US [patent_app_date] => 2001-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 6817 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0047/20010047978.pdf [firstpage_image] =>[orig_patent_app_number] => 09826135 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/826135
Process for the double-side polishing of semiconductor wafers and carrier for carrying out the process Apr 3, 2001 Issued
Array ( [id] => 7093246 [patent_doc_number] => 20010034132 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-10-25 [patent_title] => 'Method of manufacturing a semiconductor device and a semicondustor device' [patent_app_type] => new [patent_app_number] => 09/823975 [patent_app_country] => US [patent_app_date] => 2001-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 44 [patent_figures_cnt] => 44 [patent_no_of_words] => 16616 [patent_no_of_claims] => 46 [patent_no_of_ind_claims] => 21 [patent_words_short_claim] => 34 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0034/20010034132.pdf [firstpage_image] =>[orig_patent_app_number] => 09823975 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/823975
Method of manufacturing a semiconductor device and a semiconductor device Apr 2, 2001 Issued
Array ( [id] => 1576499 [patent_doc_number] => 06447688 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-09-10 [patent_title] => 'Method for fabricating a stencil mask' [patent_app_type] => B2 [patent_app_number] => 09/822460 [patent_app_country] => US [patent_app_date] => 2001-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 12 [patent_no_of_words] => 2228 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 281 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/447/06447688.pdf [firstpage_image] =>[orig_patent_app_number] => 09822460 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/822460
Method for fabricating a stencil mask Apr 1, 2001 Issued
Array ( [id] => 5906965 [patent_doc_number] => 20020142603 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-10-03 [patent_title] => 'METHOD FOR FORMING SQUARE-SHOULDERED SIDEWALL SPACERS AND DEVICES FABRICATED' [patent_app_type] => new [patent_app_number] => 09/821987 [patent_app_country] => US [patent_app_date] => 2001-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3360 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 44 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0142/20020142603.pdf [firstpage_image] =>[orig_patent_app_number] => 09821987 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/821987
Method for forming square-shouldered sidewall spacers and devices fabricated Mar 29, 2001 Issued
Array ( [id] => 6896234 [patent_doc_number] => 20010027024 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-10-04 [patent_title] => 'Method of forming a polycide electrode in a semiconductor device' [patent_app_type] => new [patent_app_number] => 09/817061 [patent_app_country] => US [patent_app_date] => 2001-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5228 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0027/20010027024.pdf [firstpage_image] =>[orig_patent_app_number] => 09817061 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/817061
Method of forming a polycide electrode in a semiconductor device Mar 26, 2001 Issued
Array ( [id] => 1418619 [patent_doc_number] => 06514867 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-02-04 [patent_title] => 'Method of creating narrow trench lines using hard mask' [patent_app_type] => B1 [patent_app_number] => 09/817586 [patent_app_country] => US [patent_app_date] => 2001-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 2066 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/514/06514867.pdf [firstpage_image] =>[orig_patent_app_number] => 09817586 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/817586
Method of creating narrow trench lines using hard mask Mar 25, 2001 Issued
Array ( [id] => 1418626 [patent_doc_number] => 06514868 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-02-04 [patent_title] => 'Method of creating a smaller contact using hard mask' [patent_app_type] => B1 [patent_app_number] => 09/817911 [patent_app_country] => US [patent_app_date] => 2001-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 2014 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/514/06514868.pdf [firstpage_image] =>[orig_patent_app_number] => 09817911 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/817911
Method of creating a smaller contact using hard mask Mar 25, 2001 Issued
Array ( [id] => 1600559 [patent_doc_number] => 06475920 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-11-05 [patent_title] => 'Plasma etching method using low ionization potential gas' [patent_app_type] => B2 [patent_app_number] => 09/812543 [patent_app_country] => US [patent_app_date] => 2001-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 5710 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/475/06475920.pdf [firstpage_image] =>[orig_patent_app_number] => 09812543 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/812543
Plasma etching method using low ionization potential gas Mar 19, 2001 Issued
Array ( [id] => 1559909 [patent_doc_number] => 06436833 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-20 [patent_title] => 'Method for pre-STI-CMP planarization using poly-si thermal oxidation' [patent_app_type] => B1 [patent_app_number] => 09/805953 [patent_app_country] => US [patent_app_date] => 2001-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 1513 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 214 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/436/06436833.pdf [firstpage_image] =>[orig_patent_app_number] => 09805953 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/805953
Method for pre-STI-CMP planarization using poly-si thermal oxidation Mar 14, 2001 Issued
Array ( [id] => 1595759 [patent_doc_number] => 06492272 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-10 [patent_title] => 'Carrier gas modification for use in plasma ashing of photoresist' [patent_app_type] => B1 [patent_app_number] => 09/805975 [patent_app_country] => US [patent_app_date] => 2001-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 4987 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/492/06492272.pdf [firstpage_image] =>[orig_patent_app_number] => 09805975 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/805975
Carrier gas modification for use in plasma ashing of photoresist Mar 14, 2001 Issued
Array ( [id] => 1409606 [patent_doc_number] => 06517735 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-02-11 [patent_title] => 'Ink feed trench etch technique for a fully integrated thermal inkjet printhead' [patent_app_type] => B2 [patent_app_number] => 09/811052 [patent_app_country] => US [patent_app_date] => 2001-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 4186 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 229 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/517/06517735.pdf [firstpage_image] =>[orig_patent_app_number] => 09811052 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/811052
Ink feed trench etch technique for a fully integrated thermal inkjet printhead Mar 14, 2001 Issued
Array ( [id] => 1495091 [patent_doc_number] => 06403484 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-11 [patent_title] => 'Method to achieve STI planarization' [patent_app_type] => B1 [patent_app_number] => 09/803187 [patent_app_country] => US [patent_app_date] => 2001-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 1765 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 241 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/403/06403484.pdf [firstpage_image] =>[orig_patent_app_number] => 09803187 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/803187
Method to achieve STI planarization Mar 11, 2001 Issued
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