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Alexander Scott Harrison

Examiner (ID: 17072, Phone: (571)270-7573 , Office: P/3636 )

Most Active Art Unit
3636
Art Unit(s)
3636
Total Applications
256
Issued Applications
177
Pending Applications
3
Abandoned Applications
76

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 20311760 [patent_doc_number] => 20250329389 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-10-23 [patent_title] => MANAGING PROGRAM DISTURB IN MEMORY DEVICES [patent_app_type] => utility [patent_app_number] => 18/770632 [patent_app_country] => US [patent_app_date] => 2024-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6764 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18770632 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/770632
MANAGING PROGRAM DISTURB IN MEMORY DEVICES Jul 10, 2024 Pending
Array ( [id] => 19835489 [patent_doc_number] => 20250087275 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-13 [patent_title] => SELECTIVELY ERASING ONE OF MULTIPLE ERASE BLOCKS COUPLED TO A SAME STRING USING GATE INDUCED DRAIN LEAKAGE [patent_app_type] => utility [patent_app_number] => 18/768970 [patent_app_country] => US [patent_app_date] => 2024-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9629 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18768970 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/768970
Selectively erasing one of multiple erase blocks coupled to a same string using gate induced drain leakage Jul 9, 2024 Issued
Array ( [id] => 19712380 [patent_doc_number] => 20250022522 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-16 [patent_title] => ELECTROCHEMICAL CHARGE STORAGE DEVICE [patent_app_type] => utility [patent_app_number] => 18/768870 [patent_app_country] => US [patent_app_date] => 2024-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9480 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18768870 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/768870
ELECTROCHEMICAL CHARGE STORAGE DEVICE Jul 9, 2024 Pending
Array ( [id] => 20482647 [patent_doc_number] => 12531123 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-01-20 [patent_title] => Non-volatile memory with auxiliary select gate line driver [patent_app_type] => utility [patent_app_number] => 18/765358 [patent_app_country] => US [patent_app_date] => 2024-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 40 [patent_no_of_words] => 4420 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 450 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18765358 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/765358
Non-volatile memory with auxiliary select gate line driver Jul 7, 2024 Issued
Array ( [id] => 19934862 [patent_doc_number] => 12308070 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-05-20 [patent_title] => Word line drivers for multiple-die memory devices [patent_app_type] => utility [patent_app_number] => 18/765076 [patent_app_country] => US [patent_app_date] => 2024-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 14028 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18765076 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/765076
Word line drivers for multiple-die memory devices Jul 4, 2024 Issued
Array ( [id] => 19515398 [patent_doc_number] => 20240347084 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-17 [patent_title] => DETERMINING READ VOLTAGE OFFSET IN MEMORY DEVICES [patent_app_type] => utility [patent_app_number] => 18/755033 [patent_app_country] => US [patent_app_date] => 2024-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10079 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18755033 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/755033
Determining read voltage offset in memory devices Jun 25, 2024 Issued
Array ( [id] => 19951084 [patent_doc_number] => 12322454 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-06-03 [patent_title] => Nonvolatile semiconductor memory device including a memory cell array and a control circuit applying a reading voltage [patent_app_type] => utility [patent_app_number] => 18/752870 [patent_app_country] => US [patent_app_date] => 2024-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 31 [patent_no_of_words] => 6320 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 300 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18752870 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/752870
Nonvolatile semiconductor memory device including a memory cell array and a control circuit applying a reading voltage Jun 24, 2024 Issued
Array ( [id] => 19687722 [patent_doc_number] => 20250006267 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-02 [patent_title] => NON-VOLATILE MEMORY AND CORRESPONDING MANUFACTURING METHOD [patent_app_type] => utility [patent_app_number] => 18/753094 [patent_app_country] => US [patent_app_date] => 2024-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7595 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18753094 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/753094
Non-volatile memory and corresponding manufacturing method Jun 24, 2024 Issued
Array ( [id] => 20311759 [patent_doc_number] => 20250329388 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-10-23 [patent_title] => MEMORY, OPERATION METHOD OF MEMORY, AND MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 18/750641 [patent_app_country] => US [patent_app_date] => 2024-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9413 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 234 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18750641 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/750641
MEMORY, OPERATION METHOD OF MEMORY, AND MEMORY SYSTEM Jun 20, 2024 Pending
Array ( [id] => 19788251 [patent_doc_number] => 20250061930 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-20 [patent_title] => Truncated Resolution for Time Sliced Computation of Multiplication and Accumulation using a Memory Cell Array [patent_app_type] => utility [patent_app_number] => 18/751094 [patent_app_country] => US [patent_app_date] => 2024-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12248 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18751094 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/751094
Truncated Resolution for Time Sliced Computation of Multiplication and Accumulation using a Memory Cell Array Jun 20, 2024 Pending
Array ( [id] => 20422850 [patent_doc_number] => 20250384935 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-12-18 [patent_title] => MEMORY DEVICE AND DATA ACCESSING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/741780 [patent_app_country] => US [patent_app_date] => 2024-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18741780 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/741780
MEMORY DEVICE AND DATA ACCESSING METHOD THEREOF Jun 12, 2024 Issued
Array ( [id] => 19749181 [patent_doc_number] => 20250037746 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-30 [patent_title] => On-Die Termination of Address and Command Signals [patent_app_type] => utility [patent_app_number] => 18/680395 [patent_app_country] => US [patent_app_date] => 2024-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3755 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18680395 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/680395
On-die termination of address and command signals May 30, 2024 Issued
Array ( [id] => 19452403 [patent_doc_number] => 20240312533 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-19 [patent_title] => MEMORY SYSTEM, CONTROL METHOD THEREOF, AND PROGRAM [patent_app_type] => utility [patent_app_number] => 18/677727 [patent_app_country] => US [patent_app_date] => 2024-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13651 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18677727 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/677727
Memory system, control method thereof, and program May 28, 2024 Issued
Array ( [id] => 20297635 [patent_doc_number] => 20250322878 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-10-16 [patent_title] => MEMORY DEVICE, MEMORY SYSTEM, AND METHOD OF OPERATING THE SAME [patent_app_type] => utility [patent_app_number] => 18/676135 [patent_app_country] => US [patent_app_date] => 2024-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2524 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18676135 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/676135
MEMORY DEVICE, MEMORY SYSTEM, AND METHOD OF OPERATING THE SAME May 27, 2024 Pending
Array ( [id] => 19926022 [patent_doc_number] => 12300314 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-05-13 [patent_title] => Memory system and memory device [patent_app_type] => utility [patent_app_number] => 18/675257 [patent_app_country] => US [patent_app_date] => 2024-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 68 [patent_figures_cnt] => 75 [patent_no_of_words] => 38695 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 209 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18675257 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/675257
Memory system and memory device May 27, 2024 Issued
Array ( [id] => 19589406 [patent_doc_number] => 20240386963 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-21 [patent_title] => PROGRAMMING TECHNIQUES FOR POLARITY-BASED MEMORY CELLS [patent_app_type] => utility [patent_app_number] => 18/664199 [patent_app_country] => US [patent_app_date] => 2024-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19793 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18664199 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/664199
Programming techniques for polarity-based memory cells May 13, 2024 Issued
Array ( [id] => 20434900 [patent_doc_number] => 12505887 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-12-23 [patent_title] => Discharge circuits for a NAND flash memory [patent_app_type] => utility [patent_app_number] => 18/663879 [patent_app_country] => US [patent_app_date] => 2024-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 16 [patent_no_of_words] => 5820 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18663879 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/663879
Discharge circuits for a NAND flash memory May 13, 2024 Issued
Array ( [id] => 19900045 [patent_doc_number] => 12277977 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-04-15 [patent_title] => ONON sidewall structure for memory device and method for making the same [patent_app_type] => utility [patent_app_number] => 18/662709 [patent_app_country] => US [patent_app_date] => 2024-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 3556 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18662709 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/662709
ONON sidewall structure for memory device and method for making the same May 12, 2024 Issued
Array ( [id] => 19420769 [patent_doc_number] => 20240296893 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-05 [patent_title] => SEMICONDUCTOR MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/662971 [patent_app_country] => US [patent_app_date] => 2024-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14159 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18662971 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/662971
Semiconductor memory device May 12, 2024 Issued
Array ( [id] => 19900037 [patent_doc_number] => 12277969 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-04-15 [patent_title] => Auto-referenced memory cell read techniques [patent_app_type] => utility [patent_app_number] => 18/661300 [patent_app_country] => US [patent_app_date] => 2024-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 13 [patent_no_of_words] => 14701 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18661300 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/661300
Auto-referenced memory cell read techniques May 9, 2024 Issued
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