Search

Alexander Sofocleous

Examiner (ID: 721)

Most Active Art Unit
2824
Art Unit(s)
2825, 2824, 2895
Total Applications
473
Issued Applications
387
Pending Applications
11
Abandoned Applications
76

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5832208 [patent_doc_number] => 20060244038 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-11-02 [patent_title] => 'Split gate flash memory cell with ballistic injection' [patent_app_type] => utility [patent_app_number] => 11/477979 [patent_app_country] => US [patent_app_date] => 2006-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3985 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0244/20060244038.pdf [firstpage_image] =>[orig_patent_app_number] => 11477979 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/477979
Split gate flash memory cell with ballistic injection Jun 28, 2006 Abandoned
Array ( [id] => 5833452 [patent_doc_number] => 20060245282 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-11-02 [patent_title] => 'Sense amplifier circuit' [patent_app_type] => utility [patent_app_number] => 11/477164 [patent_app_country] => US [patent_app_date] => 2006-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2677 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0245/20060245282.pdf [firstpage_image] =>[orig_patent_app_number] => 11477164 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/477164
Sense amplifier circuit Jun 27, 2006 Issued
Array ( [id] => 5347678 [patent_doc_number] => 20090003039 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-01-01 [patent_title] => 'Electromechanical Memory, Electric Circuit Using the Same, and Method of Driving Electromechanical Memory' [patent_app_type] => utility [patent_app_number] => 11/813568 [patent_app_country] => US [patent_app_date] => 2006-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 11012 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0003/20090003039.pdf [firstpage_image] =>[orig_patent_app_number] => 11813568 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/813568
Electromechanical memory, electric circuit using the same, and method of driving electromechanical memory Jun 20, 2006 Issued
Array ( [id] => 315856 [patent_doc_number] => 07525834 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-04-28 [patent_title] => 'SRAM cell structure and circuits' [patent_app_type] => utility [patent_app_number] => 11/471036 [patent_app_country] => US [patent_app_date] => 2006-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 14 [patent_no_of_words] => 7132 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/525/07525834.pdf [firstpage_image] =>[orig_patent_app_number] => 11471036 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/471036
SRAM cell structure and circuits Jun 18, 2006 Issued
Array ( [id] => 5209349 [patent_doc_number] => 20070247933 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-10-25 [patent_title] => 'Method of High-Performance Flash Memory Data Transfer' [patent_app_type] => utility [patent_app_number] => 11/424573 [patent_app_country] => US [patent_app_date] => 2006-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 14993 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0247/20070247933.pdf [firstpage_image] =>[orig_patent_app_number] => 11424573 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/424573
Method of high-performance flash memory data transfer Jun 15, 2006 Issued
Array ( [id] => 248027 [patent_doc_number] => 07586784 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-09-08 [patent_title] => 'Apparatus and methods for programming multilevel-cell NAND memory devices' [patent_app_type] => utility [patent_app_number] => 11/450759 [patent_app_country] => US [patent_app_date] => 2006-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4393 [patent_no_of_claims] => 54 [patent_no_of_ind_claims] => 20 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/586/07586784.pdf [firstpage_image] =>[orig_patent_app_number] => 11450759 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/450759
Apparatus and methods for programming multilevel-cell NAND memory devices Jun 8, 2006 Issued
Array ( [id] => 349847 [patent_doc_number] => 07495970 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-02-24 [patent_title] => 'Flexible memory architectures for programmable logic devices' [patent_app_type] => utility [patent_app_number] => 11/446309 [patent_app_country] => US [patent_app_date] => 2006-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 7938 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/495/07495970.pdf [firstpage_image] =>[orig_patent_app_number] => 11446309 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/446309
Flexible memory architectures for programmable logic devices Jun 1, 2006 Issued
Array ( [id] => 5044772 [patent_doc_number] => 20070263444 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-11-15 [patent_title] => 'Non-Volatile Memory System with End of Life Calculation' [patent_app_type] => utility [patent_app_number] => 11/383397 [patent_app_country] => US [patent_app_date] => 2006-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7503 [patent_no_of_claims] => 62 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0263/20070263444.pdf [firstpage_image] =>[orig_patent_app_number] => 11383397 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/383397
Non-volatile memory system with end of life calculation May 14, 2006 Issued
Array ( [id] => 5782305 [patent_doc_number] => 20060203554 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-09-14 [patent_title] => 'Multi-state memory cell with asymmetric charge trapping' [patent_app_type] => utility [patent_app_number] => 11/432019 [patent_app_country] => US [patent_app_date] => 2006-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3082 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0203/20060203554.pdf [firstpage_image] =>[orig_patent_app_number] => 11432019 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/432019
Multi-state memory cell with asymmetric charge trapping May 10, 2006 Issued
Array ( [id] => 5782306 [patent_doc_number] => 20060203555 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-09-14 [patent_title] => 'Multi-state memory cell with asymmetric charge trapping' [patent_app_type] => utility [patent_app_number] => 11/432020 [patent_app_country] => US [patent_app_date] => 2006-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3085 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0203/20060203555.pdf [firstpage_image] =>[orig_patent_app_number] => 11432020 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/432020
Multi-state memory cell with asymmetric charge trapping May 10, 2006 Issued
Array ( [id] => 811804 [patent_doc_number] => 07417901 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-08-26 [patent_title] => 'Memory device having terminals for transferring multiple types of data' [patent_app_type] => utility [patent_app_number] => 11/382649 [patent_app_country] => US [patent_app_date] => 2006-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 9427 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/417/07417901.pdf [firstpage_image] =>[orig_patent_app_number] => 11382649 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/382649
Memory device having terminals for transferring multiple types of data May 9, 2006 Issued
Array ( [id] => 422669 [patent_doc_number] => 07274604 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-09-25 [patent_title] => 'Memory device having terminals for transferring multiple types of data' [patent_app_type] => utility [patent_app_number] => 11/382641 [patent_app_country] => US [patent_app_date] => 2006-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 9433 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/274/07274604.pdf [firstpage_image] =>[orig_patent_app_number] => 11382641 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/382641
Memory device having terminals for transferring multiple types of data May 9, 2006 Issued
Array ( [id] => 331521 [patent_doc_number] => 07512021 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-03-31 [patent_title] => 'Register configuration control device, register configuration control method, and program for implementing the method' [patent_app_type] => utility [patent_app_number] => 11/429033 [patent_app_country] => US [patent_app_date] => 2006-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 24 [patent_no_of_words] => 13012 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/512/07512021.pdf [firstpage_image] =>[orig_patent_app_number] => 11429033 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/429033
Register configuration control device, register configuration control method, and program for implementing the method May 4, 2006 Issued
Array ( [id] => 5224048 [patent_doc_number] => 20070253314 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-11-01 [patent_title] => 'Low surface energy coatings in probe recording' [patent_app_type] => utility [patent_app_number] => 11/414893 [patent_app_country] => US [patent_app_date] => 2006-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2371 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0253/20070253314.pdf [firstpage_image] =>[orig_patent_app_number] => 11414893 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/414893
Low surface energy coatings in probe recording Apr 30, 2006 Issued
Array ( [id] => 6286136 [patent_doc_number] => 20100157662 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-06-24 [patent_title] => 'MRAM AND METHOD FOR WRITING IN MRAM' [patent_app_type] => utility [patent_app_number] => 11/919189 [patent_app_country] => US [patent_app_date] => 2006-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7042 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 17 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0157/20100157662.pdf [firstpage_image] =>[orig_patent_app_number] => 11919189 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/919189
MRAM AND METHOD FOR WRITING IN MRAM Apr 25, 2006 Abandoned
Array ( [id] => 588515 [patent_doc_number] => 07457174 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-11-25 [patent_title] => 'Semiconductor memory and method for adapting the phase relationship between a clock signal and strobe signal during the acceptance of write data to be transmitted' [patent_app_type] => utility [patent_app_number] => 11/410320 [patent_app_country] => US [patent_app_date] => 2006-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7190 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/457/07457174.pdf [firstpage_image] =>[orig_patent_app_number] => 11410320 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/410320
Semiconductor memory and method for adapting the phase relationship between a clock signal and strobe signal during the acceptance of write data to be transmitted Apr 23, 2006 Issued
Array ( [id] => 5618174 [patent_doc_number] => 20060187707 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-08-24 [patent_title] => 'Non-volatile memory array with simultaneous write and erase feature' [patent_app_type] => utility [patent_app_number] => 11/407568 [patent_app_country] => US [patent_app_date] => 2006-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4269 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0187/20060187707.pdf [firstpage_image] =>[orig_patent_app_number] => 11407568 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/407568
Non-volatile memory array with simultaneous write and erase feature Apr 18, 2006 Abandoned
Array ( [id] => 5704135 [patent_doc_number] => 20060193183 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-08-31 [patent_title] => 'Reducing DQ pin capacitance in a memory device' [patent_app_type] => utility [patent_app_number] => 11/406643 [patent_app_country] => US [patent_app_date] => 2006-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6258 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0193/20060193183.pdf [firstpage_image] =>[orig_patent_app_number] => 11406643 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/406643
Reducing DQ pin capacitance in a memory device Apr 18, 2006 Issued
Array ( [id] => 542702 [patent_doc_number] => 07180771 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-02-20 [patent_title] => 'Device and method for pulse width control in a phase change memory device' [patent_app_type] => utility [patent_app_number] => 11/405993 [patent_app_country] => US [patent_app_date] => 2006-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 17 [patent_no_of_words] => 6061 [patent_no_of_claims] => 55 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/180/07180771.pdf [firstpage_image] =>[orig_patent_app_number] => 11405993 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/405993
Device and method for pulse width control in a phase change memory device Apr 17, 2006 Issued
Array ( [id] => 297047 [patent_doc_number] => 07542324 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-06-02 [patent_title] => 'FPGA equivalent input and output grid muxing on structural ASIC memory' [patent_app_type] => utility [patent_app_number] => 11/405807 [patent_app_country] => US [patent_app_date] => 2006-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 6087 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/542/07542324.pdf [firstpage_image] =>[orig_patent_app_number] => 11405807 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/405807
FPGA equivalent input and output grid muxing on structural ASIC memory Apr 16, 2006 Issued
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