Search

Alexander Sofocleous

Examiner (ID: 721)

Most Active Art Unit
2824
Art Unit(s)
2825, 2824, 2895
Total Applications
473
Issued Applications
387
Pending Applications
11
Abandoned Applications
76

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6968 [patent_doc_number] => 07813160 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-10-12 [patent_title] => 'Nanocrystal quantum dot memory devices' [patent_app_type] => utility [patent_app_number] => 11/329471 [patent_app_country] => US [patent_app_date] => 2006-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 30 [patent_no_of_words] => 9996 [patent_no_of_claims] => 44 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/813/07813160.pdf [firstpage_image] =>[orig_patent_app_number] => 11329471 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/329471
Nanocrystal quantum dot memory devices Jan 10, 2006 Issued
Array ( [id] => 5217497 [patent_doc_number] => 20070158808 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-07-12 [patent_title] => 'Multiple chip module and package stacking method for storage devices' [patent_app_type] => utility [patent_app_number] => 11/322442 [patent_app_country] => US [patent_app_date] => 2005-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 29 [patent_no_of_words] => 5488 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0158/20070158808.pdf [firstpage_image] =>[orig_patent_app_number] => 11322442 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/322442
Multiple chip module and package stacking for storage devices Dec 28, 2005 Issued
Array ( [id] => 225868 [patent_doc_number] => 07606056 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-10-20 [patent_title] => 'Process for manufacturing a phase change memory array in Cu-damascene technology and phase change memory array thereby manufactured' [patent_app_type] => utility [patent_app_number] => 11/317622 [patent_app_country] => US [patent_app_date] => 2005-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 19 [patent_no_of_words] => 3451 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/606/07606056.pdf [firstpage_image] =>[orig_patent_app_number] => 11317622 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/317622
Process for manufacturing a phase change memory array in Cu-damascene technology and phase change memory array thereby manufactured Dec 21, 2005 Issued
Array ( [id] => 588529 [patent_doc_number] => 07457177 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-11-25 [patent_title] => 'Random access memory including circuit to compress comparison results' [patent_app_type] => utility [patent_app_number] => 11/314605 [patent_app_country] => US [patent_app_date] => 2005-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 11894 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/457/07457177.pdf [firstpage_image] =>[orig_patent_app_number] => 11314605 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/314605
Random access memory including circuit to compress comparison results Dec 20, 2005 Issued
Array ( [id] => 5116806 [patent_doc_number] => 20070138520 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-06-21 [patent_title] => 'Ferroelectric passive memory cell, device and method of manufacture thereof' [patent_app_type] => utility [patent_app_number] => 11/313153 [patent_app_country] => US [patent_app_date] => 2005-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 15494 [patent_no_of_claims] => 45 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0138/20070138520.pdf [firstpage_image] =>[orig_patent_app_number] => 11313153 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/313153
Ferroelectric passive memory cell, device and method of manufacture thereof Dec 19, 2005 Issued
Array ( [id] => 4435840 [patent_doc_number] => 07969762 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-06-28 [patent_title] => 'Spintronic device with control by domain wall displacement induced by a current of spin-polarized carriers' [patent_app_type] => utility [patent_app_number] => 11/721950 [patent_app_country] => US [patent_app_date] => 2005-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 17 [patent_no_of_words] => 4642 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 233 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/969/07969762.pdf [firstpage_image] =>[orig_patent_app_number] => 11721950 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/721950
Spintronic device with control by domain wall displacement induced by a current of spin-polarized carriers Dec 13, 2005 Issued
Array ( [id] => 906038 [patent_doc_number] => 07336527 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-02-26 [patent_title] => 'Electromechanical storage device' [patent_app_type] => utility [patent_app_number] => 11/300709 [patent_app_country] => US [patent_app_date] => 2005-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 35 [patent_no_of_words] => 8873 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/336/07336527.pdf [firstpage_image] =>[orig_patent_app_number] => 11300709 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/300709
Electromechanical storage device Dec 13, 2005 Issued
Array ( [id] => 244281 [patent_doc_number] => 07590020 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-09-15 [patent_title] => 'Semiconductor memory, semiconductor memory system and method of monitoring dynamic temperature thereof' [patent_app_type] => utility [patent_app_number] => 11/302439 [patent_app_country] => US [patent_app_date] => 2005-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5491 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/590/07590020.pdf [firstpage_image] =>[orig_patent_app_number] => 11302439 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/302439
Semiconductor memory, semiconductor memory system and method of monitoring dynamic temperature thereof Dec 13, 2005 Issued
Array ( [id] => 360655 [patent_doc_number] => 07486534 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-02-03 [patent_title] => 'Diode-less array for one-time programmable memory' [patent_app_type] => utility [patent_app_number] => 11/297529 [patent_app_country] => US [patent_app_date] => 2005-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 4137 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/486/07486534.pdf [firstpage_image] =>[orig_patent_app_number] => 11297529 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/297529
Diode-less array for one-time programmable memory Dec 7, 2005 Issued
Array ( [id] => 338986 [patent_doc_number] => 07505331 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-03-17 [patent_title] => 'Programmable logic device with differential communications support' [patent_app_type] => utility [patent_app_number] => 11/286165 [patent_app_country] => US [patent_app_date] => 2005-11-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 9272 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/505/07505331.pdf [firstpage_image] =>[orig_patent_app_number] => 11286165 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/286165
Programmable logic device with differential communications support Nov 22, 2005 Issued
Array ( [id] => 818412 [patent_doc_number] => 07411853 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-08-12 [patent_title] => 'Volatile memory elements with elevated power supply levels for programmable logic device integrated circuits' [patent_app_type] => utility [patent_app_number] => 11/282437 [patent_app_country] => US [patent_app_date] => 2005-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 7388 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/411/07411853.pdf [firstpage_image] =>[orig_patent_app_number] => 11282437 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/282437
Volatile memory elements with elevated power supply levels for programmable logic device integrated circuits Nov 16, 2005 Issued
Array ( [id] => 5657655 [patent_doc_number] => 20060143391 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-06-29 [patent_title] => 'Computer device' [patent_app_type] => utility [patent_app_number] => 11/280937 [patent_app_country] => US [patent_app_date] => 2005-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3863 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0143/20060143391.pdf [firstpage_image] =>[orig_patent_app_number] => 11280937 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/280937
Computer device Nov 14, 2005 Abandoned
Array ( [id] => 5660247 [patent_doc_number] => 20060250843 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-11-09 [patent_title] => 'Non-volatile-shadow latch using a nanotube switch' [patent_app_type] => utility [patent_app_number] => 11/280599 [patent_app_country] => US [patent_app_date] => 2005-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 29 [patent_no_of_words] => 22206 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0250/20060250843.pdf [firstpage_image] =>[orig_patent_app_number] => 11280599 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/280599
Non-volatile-shadow latch using a nanotube switch Nov 14, 2005 Issued
Array ( [id] => 279026 [patent_doc_number] => 07558108 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-07-07 [patent_title] => '3-bit NROM flash and method of operating same' [patent_app_type] => utility [patent_app_number] => 11/265767 [patent_app_country] => US [patent_app_date] => 2005-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4677 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 303 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/558/07558108.pdf [firstpage_image] =>[orig_patent_app_number] => 11265767 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/265767
3-bit NROM flash and method of operating same Oct 31, 2005 Issued
Array ( [id] => 5039387 [patent_doc_number] => 20070091669 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-04-26 [patent_title] => 'Giant magneto-resistive static read RAM memory architecture' [patent_app_type] => utility [patent_app_number] => 11/257327 [patent_app_country] => US [patent_app_date] => 2005-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3647 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0091/20070091669.pdf [firstpage_image] =>[orig_patent_app_number] => 11257327 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/257327
Complementary giant magneto-resistive memory with full-turn word line Oct 23, 2005 Issued
Array ( [id] => 586085 [patent_doc_number] => 07460431 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-12-02 [patent_title] => 'Implementation of double data rate embedded memory in programmable devices' [patent_app_type] => utility [patent_app_number] => 11/242693 [patent_app_country] => US [patent_app_date] => 2005-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7847 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/460/07460431.pdf [firstpage_image] =>[orig_patent_app_number] => 11242693 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/242693
Implementation of double data rate embedded memory in programmable devices Oct 2, 2005 Issued
Array ( [id] => 850411 [patent_doc_number] => 07382648 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-06-03 [patent_title] => 'Nanomechanical switching device' [patent_app_type] => utility [patent_app_number] => 11/239355 [patent_app_country] => US [patent_app_date] => 2005-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 5626 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/382/07382648.pdf [firstpage_image] =>[orig_patent_app_number] => 11239355 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/239355
Nanomechanical switching device Sep 29, 2005 Issued
Array ( [id] => 588987 [patent_doc_number] => 07453716 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-11-18 [patent_title] => 'Semiconductor memory device with stacked control transistors' [patent_app_type] => utility [patent_app_number] => 11/238381 [patent_app_country] => US [patent_app_date] => 2005-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 20 [patent_no_of_words] => 5463 [patent_no_of_claims] => 41 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/453/07453716.pdf [firstpage_image] =>[orig_patent_app_number] => 11238381 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/238381
Semiconductor memory device with stacked control transistors Sep 28, 2005 Issued
Array ( [id] => 5171014 [patent_doc_number] => 20070071445 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-03-29 [patent_title] => 'Method, apparatus and system for N-dimensional sparse memory using serial optical memory' [patent_app_type] => utility [patent_app_number] => 11/239535 [patent_app_country] => US [patent_app_date] => 2005-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1749 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0071/20070071445.pdf [firstpage_image] =>[orig_patent_app_number] => 11239535 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/239535
Method, apparatus and system for N-dimensional sparse memory using serial optical memory Sep 27, 2005 Issued
Array ( [id] => 5193303 [patent_doc_number] => 20070081785 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-04-12 [patent_title] => 'Method, apparatus and system for global shared memory using serial optical memory' [patent_app_type] => utility [patent_app_number] => 11/238490 [patent_app_country] => US [patent_app_date] => 2005-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1766 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0081/20070081785.pdf [firstpage_image] =>[orig_patent_app_number] => 11238490 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/238490
Method, apparatus and system for global shared memory using serial optical memory Sep 27, 2005 Issued
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