
Alexander Sofocleous
Examiner (ID: 721)
| Most Active Art Unit | 2824 |
| Art Unit(s) | 2825, 2824, 2895 |
| Total Applications | 473 |
| Issued Applications | 387 |
| Pending Applications | 11 |
| Abandoned Applications | 76 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 5811274
[patent_doc_number] => 20060082383
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-04-20
[patent_title] => 'Pseudo differential output buffer, memory chip and memory system'
[patent_app_type] => utility
[patent_app_number] => 11/226263
[patent_app_country] => US
[patent_app_date] => 2005-09-15
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[patent_no_of_words] => 3353
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[pdf_file] => publications/A1/0082/20060082383.pdf
[firstpage_image] =>[orig_patent_app_number] => 11226263
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/226263 | Pseudo differential output buffer, memory chip and memory system | Sep 14, 2005 | Issued |
Array
(
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[patent_doc_number] => 20070058409
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[patent_kind] => A1
[patent_issue_date] => 2007-03-15
[patent_title] => 'Semiconductor memory arrangement with branched control and address bus'
[patent_app_type] => utility
[patent_app_number] => 11/226448
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Array
(
[id] => 5055519
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[patent_kind] => A1
[patent_issue_date] => 2007-03-15
[patent_title] => 'Hole annealing methods of non-volatile memory cells'
[patent_app_type] => utility
[patent_app_number] => 11/224597
[patent_app_country] => US
[patent_app_date] => 2005-09-12
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[firstpage_image] =>[orig_patent_app_number] => 11224597
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/224597 | Hole annealing methods of non-volatile memory cells | Sep 11, 2005 | Issued |
Array
(
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[patent_doc_number] => 07372760
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-05-13
[patent_title] => 'Semiconductor device and entry into test mode without use of unnecessary terminal'
[patent_app_type] => utility
[patent_app_number] => 11/207935
[patent_app_country] => US
[patent_app_date] => 2005-08-22
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[pdf_file] => patents/07/372/07372760.pdf
[firstpage_image] =>[orig_patent_app_number] => 11207935
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/207935 | Semiconductor device and entry into test mode without use of unnecessary terminal | Aug 21, 2005 | Issued |
Array
(
[id] => 187082
[patent_doc_number] => 07646630
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-01-12
[patent_title] => 'Programmable matrix array with chalcogenide material'
[patent_app_type] => utility
[patent_app_number] => 11/209079
[patent_app_country] => US
[patent_app_date] => 2005-08-22
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[patent_drawing_sheets_cnt] => 41
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[pdf_file] => patents/07/646/07646630.pdf
[firstpage_image] =>[orig_patent_app_number] => 11209079
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/209079 | Programmable matrix array with chalcogenide material | Aug 21, 2005 | Issued |
Array
(
[id] => 4998623
[patent_doc_number] => 20070041257
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-02-22
[patent_title] => 'Low voltage sensing scheme having reduced active power down standby current'
[patent_app_type] => utility
[patent_app_number] => 11/205659
[patent_app_country] => US
[patent_app_date] => 2005-08-17
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[pdf_file] => publications/A1/0041/20070041257.pdf
[firstpage_image] =>[orig_patent_app_number] => 11205659
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/205659 | Low voltage sensing scheme having reduced active power down standby current | Aug 16, 2005 | Issued |
Array
(
[id] => 5797893
[patent_doc_number] => 20060034132
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[patent_title] => 'Synchronous SRAM capable of faster read-modify-write operation'
[patent_app_type] => utility
[patent_app_number] => 11/195337
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[patent_app_date] => 2005-08-02
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[pdf_file] => publications/A1/0034/20060034132.pdf
[firstpage_image] =>[orig_patent_app_number] => 11195337
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/195337 | Synchronous SRAM capable of faster read-modify-write operation | Aug 1, 2005 | Issued |
Array
(
[id] => 377934
[patent_doc_number] => 07313038
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-12-25
[patent_title] => 'Nonvolatile memory including a verify circuit'
[patent_app_type] => utility
[patent_app_number] => 11/191973
[patent_app_country] => US
[patent_app_date] => 2005-07-29
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[pdf_file] => patents/07/313/07313038.pdf
[firstpage_image] =>[orig_patent_app_number] => 11191973
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/191973 | Nonvolatile memory including a verify circuit | Jul 28, 2005 | Issued |
Array
(
[id] => 815068
[patent_doc_number] => 07414917
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-08-19
[patent_title] => 'Re-driving CAwD and rD signal lines'
[patent_app_type] => utility
[patent_app_number] => 11/192335
[patent_app_country] => US
[patent_app_date] => 2005-07-29
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[pdf_file] => patents/07/414/07414917.pdf
[firstpage_image] =>[orig_patent_app_number] => 11192335
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/192335 | Re-driving CAwD and rD signal lines | Jul 28, 2005 | Issued |
Array
(
[id] => 499128
[patent_doc_number] => 07212461
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-05-01
[patent_title] => 'Semiconductor memory device'
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[patent_app_number] => 11/193145
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[patent_app_date] => 2005-07-27
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[pdf_file] => patents/07/212/07212461.pdf
[firstpage_image] =>[orig_patent_app_number] => 11193145
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/193145 | Semiconductor memory device | Jul 26, 2005 | Issued |
Array
(
[id] => 478611
[patent_doc_number] => 07227781
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[patent_kind] => B2
[patent_issue_date] => 2007-06-05
[patent_title] => 'Semiconductor device provided with NAND strings and select gates having different gate lengths'
[patent_app_type] => utility
[patent_app_number] => 11/190005
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[pdf_file] => patents/07/227/07227781.pdf
[firstpage_image] =>[orig_patent_app_number] => 11190005
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/190005 | Semiconductor device provided with NAND strings and select gates having different gate lengths | Jul 26, 2005 | Issued |
Array
(
[id] => 5239730
[patent_doc_number] => 20070018221
[patent_country] => US
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[patent_issue_date] => 2007-01-25
[patent_title] => 'Programmable structure including discontinuous storage elements and spacer control gates in a trench'
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[patent_app_number] => 11/188585
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/188585 | Programmable structure including discontinuous storage elements and spacer control gates in a trench | Jul 24, 2005 | Issued |
Array
(
[id] => 5856434
[patent_doc_number] => 20060227637
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[patent_title] => 'Equalizer and method thereof and memory device'
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[firstpage_image] =>[orig_patent_app_number] => 11188041
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/188041 | Equalizer and method thereof and memory device | Jul 21, 2005 | Abandoned |
Array
(
[id] => 455597
[patent_doc_number] => 07248519
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[patent_title] => 'Semiconductor device that initializes memory cells of an activated wordline group'
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Array
(
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[patent_title] => 'Multilevel phase-change memory element and operating method'
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Array
(
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[patent_title] => 'Switchable resistive memory with opposite polarity write pulses'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/179122 | Switchable resistive memory with opposite polarity write pulses | Jul 10, 2005 | Issued |
Array
(
[id] => 542788
[patent_doc_number] => 07180779
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/178965 | Memory architecture with enhanced over-erase tolerant control gate scheme | Jul 10, 2005 | Issued |
Array
(
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Array
(
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[patent_title] => 'Memory module decoder'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/173175 | Memory module decoder | Jun 30, 2005 | Issued |
Array
(
[id] => 7602640
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[patent_title] => 'Area efficient implementation of small blocks in an SRAM array'
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[pdf_file] => patents/07/236/07236396.pdf
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/171033 | Area efficient implementation of small blocks in an SRAM array | Jun 29, 2005 | Issued |