Search

Alexander Sofocleous

Examiner (ID: 721)

Most Active Art Unit
2824
Art Unit(s)
2825, 2824, 2895
Total Applications
473
Issued Applications
387
Pending Applications
11
Abandoned Applications
76

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5811274 [patent_doc_number] => 20060082383 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-04-20 [patent_title] => 'Pseudo differential output buffer, memory chip and memory system' [patent_app_type] => utility [patent_app_number] => 11/226263 [patent_app_country] => US [patent_app_date] => 2005-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3353 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0082/20060082383.pdf [firstpage_image] =>[orig_patent_app_number] => 11226263 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/226263
Pseudo differential output buffer, memory chip and memory system Sep 14, 2005 Issued
Array ( [id] => 5055488 [patent_doc_number] => 20070058409 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-03-15 [patent_title] => 'Semiconductor memory arrangement with branched control and address bus' [patent_app_type] => utility [patent_app_number] => 11/226448 [patent_app_country] => US [patent_app_date] => 2005-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4994 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0058/20070058409.pdf [firstpage_image] =>[orig_patent_app_number] => 11226448 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/226448
Semiconductor memory arrangement with branched control and address bus Sep 14, 2005 Issued
Array ( [id] => 5055519 [patent_doc_number] => 20070058440 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-03-15 [patent_title] => 'Hole annealing methods of non-volatile memory cells' [patent_app_type] => utility [patent_app_number] => 11/224597 [patent_app_country] => US [patent_app_date] => 2005-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 5699 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0058/20070058440.pdf [firstpage_image] =>[orig_patent_app_number] => 11224597 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/224597
Hole annealing methods of non-volatile memory cells Sep 11, 2005 Issued
Array ( [id] => 862622 [patent_doc_number] => 07372760 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-05-13 [patent_title] => 'Semiconductor device and entry into test mode without use of unnecessary terminal' [patent_app_type] => utility [patent_app_number] => 11/207935 [patent_app_country] => US [patent_app_date] => 2005-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5339 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/372/07372760.pdf [firstpage_image] =>[orig_patent_app_number] => 11207935 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/207935
Semiconductor device and entry into test mode without use of unnecessary terminal Aug 21, 2005 Issued
Array ( [id] => 187082 [patent_doc_number] => 07646630 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-01-12 [patent_title] => 'Programmable matrix array with chalcogenide material' [patent_app_type] => utility [patent_app_number] => 11/209079 [patent_app_country] => US [patent_app_date] => 2005-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 41 [patent_figures_cnt] => 76 [patent_no_of_words] => 35759 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/646/07646630.pdf [firstpage_image] =>[orig_patent_app_number] => 11209079 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/209079
Programmable matrix array with chalcogenide material Aug 21, 2005 Issued
Array ( [id] => 4998623 [patent_doc_number] => 20070041257 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-02-22 [patent_title] => 'Low voltage sensing scheme having reduced active power down standby current' [patent_app_type] => utility [patent_app_number] => 11/205659 [patent_app_country] => US [patent_app_date] => 2005-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 9114 [patent_no_of_claims] => 43 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0041/20070041257.pdf [firstpage_image] =>[orig_patent_app_number] => 11205659 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/205659
Low voltage sensing scheme having reduced active power down standby current Aug 16, 2005 Issued
Array ( [id] => 5797893 [patent_doc_number] => 20060034132 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-02-16 [patent_title] => 'Synchronous SRAM capable of faster read-modify-write operation' [patent_app_type] => utility [patent_app_number] => 11/195337 [patent_app_country] => US [patent_app_date] => 2005-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3071 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0034/20060034132.pdf [firstpage_image] =>[orig_patent_app_number] => 11195337 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/195337
Synchronous SRAM capable of faster read-modify-write operation Aug 1, 2005 Issued
Array ( [id] => 377934 [patent_doc_number] => 07313038 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-12-25 [patent_title] => 'Nonvolatile memory including a verify circuit' [patent_app_type] => utility [patent_app_number] => 11/191973 [patent_app_country] => US [patent_app_date] => 2005-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 6305 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/313/07313038.pdf [firstpage_image] =>[orig_patent_app_number] => 11191973 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/191973
Nonvolatile memory including a verify circuit Jul 28, 2005 Issued
Array ( [id] => 815068 [patent_doc_number] => 07414917 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-08-19 [patent_title] => 'Re-driving CAwD and rD signal lines' [patent_app_type] => utility [patent_app_number] => 11/192335 [patent_app_country] => US [patent_app_date] => 2005-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3002 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 327 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/414/07414917.pdf [firstpage_image] =>[orig_patent_app_number] => 11192335 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/192335
Re-driving CAwD and rD signal lines Jul 28, 2005 Issued
Array ( [id] => 499128 [patent_doc_number] => 07212461 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-05-01 [patent_title] => 'Semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 11/193145 [patent_app_country] => US [patent_app_date] => 2005-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 2909 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/212/07212461.pdf [firstpage_image] =>[orig_patent_app_number] => 11193145 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/193145
Semiconductor memory device Jul 26, 2005 Issued
Array ( [id] => 478611 [patent_doc_number] => 07227781 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-06-05 [patent_title] => 'Semiconductor device provided with NAND strings and select gates having different gate lengths' [patent_app_type] => utility [patent_app_number] => 11/190005 [patent_app_country] => US [patent_app_date] => 2005-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3744 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/227/07227781.pdf [firstpage_image] =>[orig_patent_app_number] => 11190005 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/190005
Semiconductor device provided with NAND strings and select gates having different gate lengths Jul 26, 2005 Issued
Array ( [id] => 5239730 [patent_doc_number] => 20070018221 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-01-25 [patent_title] => 'Programmable structure including discontinuous storage elements and spacer control gates in a trench' [patent_app_type] => utility [patent_app_number] => 11/188585 [patent_app_country] => US [patent_app_date] => 2005-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5562 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0018/20070018221.pdf [firstpage_image] =>[orig_patent_app_number] => 11188585 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/188585
Programmable structure including discontinuous storage elements and spacer control gates in a trench Jul 24, 2005 Issued
Array ( [id] => 5856434 [patent_doc_number] => 20060227637 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-10-12 [patent_title] => 'Equalizer and method thereof and memory device' [patent_app_type] => utility [patent_app_number] => 11/188041 [patent_app_country] => US [patent_app_date] => 2005-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2318 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0227/20060227637.pdf [firstpage_image] =>[orig_patent_app_number] => 11188041 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/188041
Equalizer and method thereof and memory device Jul 21, 2005 Abandoned
Array ( [id] => 455597 [patent_doc_number] => 07248519 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-07-24 [patent_title] => 'Semiconductor device that initializes memory cells of an activated wordline group' [patent_app_type] => utility [patent_app_number] => 11/188055 [patent_app_country] => US [patent_app_date] => 2005-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3216 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/248/07248519.pdf [firstpage_image] =>[orig_patent_app_number] => 11188055 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/188055
Semiconductor device that initializes memory cells of an activated wordline group Jul 21, 2005 Issued
Array ( [id] => 449067 [patent_doc_number] => 07254059 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-08-07 [patent_title] => 'Multilevel phase-change memory element and operating method' [patent_app_type] => utility [patent_app_number] => 11/182783 [patent_app_country] => US [patent_app_date] => 2005-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 30 [patent_no_of_words] => 5302 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/254/07254059.pdf [firstpage_image] =>[orig_patent_app_number] => 11182783 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/182783
Multilevel phase-change memory element and operating method Jul 17, 2005 Issued
Array ( [id] => 800975 [patent_doc_number] => 07426128 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-09-16 [patent_title] => 'Switchable resistive memory with opposite polarity write pulses' [patent_app_type] => utility [patent_app_number] => 11/179122 [patent_app_country] => US [patent_app_date] => 2005-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 27 [patent_no_of_words] => 9598 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/426/07426128.pdf [firstpage_image] =>[orig_patent_app_number] => 11179122 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/179122
Switchable resistive memory with opposite polarity write pulses Jul 10, 2005 Issued
Array ( [id] => 542788 [patent_doc_number] => 07180779 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-02-20 [patent_title] => 'Memory architecture with enhanced over-erase tolerant control gate scheme' [patent_app_type] => utility [patent_app_number] => 11/178965 [patent_app_country] => US [patent_app_date] => 2005-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2975 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/180/07180779.pdf [firstpage_image] =>[orig_patent_app_number] => 11178965 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/178965
Memory architecture with enhanced over-erase tolerant control gate scheme Jul 10, 2005 Issued
Array ( [id] => 5911333 [patent_doc_number] => 20060126395 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-06-15 [patent_title] => 'Non-volatile memory cell and operating method thereof' [patent_app_type] => utility [patent_app_number] => 11/180093 [patent_app_country] => US [patent_app_date] => 2005-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3809 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0126/20060126395.pdf [firstpage_image] =>[orig_patent_app_number] => 11180093 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/180093
Non-volatile memory cell and operating method thereof Jul 10, 2005 Abandoned
Array ( [id] => 5825351 [patent_doc_number] => 20060062047 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-03-23 [patent_title] => 'Memory module decoder' [patent_app_type] => utility [patent_app_number] => 11/173175 [patent_app_country] => US [patent_app_date] => 2005-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 15936 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0062/20060062047.pdf [firstpage_image] =>[orig_patent_app_number] => 11173175 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/173175
Memory module decoder Jun 30, 2005 Issued
Array ( [id] => 7602640 [patent_doc_number] => 07236396 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-06-26 [patent_title] => 'Area efficient implementation of small blocks in an SRAM array' [patent_app_type] => utility [patent_app_number] => 11/171033 [patent_app_country] => US [patent_app_date] => 2005-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 20 [patent_no_of_words] => 8689 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/236/07236396.pdf [firstpage_image] =>[orig_patent_app_number] => 11171033 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/171033
Area efficient implementation of small blocks in an SRAM array Jun 29, 2005 Issued
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