
Alexander Sofocleous
Examiner (ID: 721)
| Most Active Art Unit | 2824 |
| Art Unit(s) | 2825, 2824, 2895 |
| Total Applications | 473 |
| Issued Applications | 387 |
| Pending Applications | 11 |
| Abandoned Applications | 76 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 5698775
[patent_doc_number] => 20060215459
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-09-28
[patent_title] => 'Active and Passive Programming/Erasing Time and Verifiable Reading for Memory System'
[patent_app_type] => utility
[patent_app_number] => 10/907225
[patent_app_country] => US
[patent_app_date] => 2005-03-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 1359
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 2
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[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0215/20060215459.pdf
[firstpage_image] =>[orig_patent_app_number] => 10907225
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/907225 | Active and Passive Programming/Erasing Time and Verifiable Reading for Memory System | Mar 23, 2005 | Abandoned |
Array
(
[id] => 498835
[patent_doc_number] => 07212424
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-05-01
[patent_title] => 'Double-high DIMM with dual registers and related methods'
[patent_app_type] => utility
[patent_app_number] => 11/085693
[patent_app_country] => US
[patent_app_date] => 2005-03-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 16
[patent_no_of_words] => 3771
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 87
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/212/07212424.pdf
[firstpage_image] =>[orig_patent_app_number] => 11085693
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/085693 | Double-high DIMM with dual registers and related methods | Mar 20, 2005 | Issued |
Array
(
[id] => 114170
[patent_doc_number] => 07719881
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-05-18
[patent_title] => 'Reconfigurable digital logic unit'
[patent_app_type] => utility
[patent_app_number] => 10/592539
[patent_app_country] => US
[patent_app_date] => 2005-03-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 4
[patent_no_of_words] => 2267
[patent_no_of_claims] => 21
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[patent_words_short_claim] => 108
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/719/07719881.pdf
[firstpage_image] =>[orig_patent_app_number] => 10592539
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/592539 | Reconfigurable digital logic unit | Mar 6, 2005 | Issued |
Array
(
[id] => 5197139
[patent_doc_number] => 20070296457
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-12-27
[patent_title] => 'Programmable Logic Circuit Control Apparatus, Programmable Logic Circuit Control Method and Program'
[patent_app_type] => utility
[patent_app_number] => 10/598151
[patent_app_country] => US
[patent_app_date] => 2005-02-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 9942
[patent_no_of_claims] => 13
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[patent_words_short_claim] => 0
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[patent_no_of_assignments] => 0
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[pdf_file] => publications/A1/0296/20070296457.pdf
[firstpage_image] =>[orig_patent_app_number] => 10598151
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/598151 | Programmable Logic Circuit Control Apparatus, Programmable Logic Circuit Control Method and Program | Feb 20, 2005 | Abandoned |
Array
(
[id] => 887768
[patent_doc_number] => 07352631
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-04-01
[patent_title] => 'Methods for programming a floating body nonvolatile memory'
[patent_app_type] => utility
[patent_app_number] => 11/061005
[patent_app_country] => US
[patent_app_date] => 2005-02-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 14
[patent_no_of_words] => 7554
[patent_no_of_claims] => 18
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/352/07352631.pdf
[firstpage_image] =>[orig_patent_app_number] => 11061005
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/061005 | Methods for programming a floating body nonvolatile memory | Feb 17, 2005 | Issued |
Array
(
[id] => 6911080
[patent_doc_number] => 20050174838
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-08-11
[patent_title] => 'MRAM memory cell having a weak intrinsic anisotropic storage layer and method of producing the same'
[patent_app_type] => utility
[patent_app_number] => 11/051471
[patent_app_country] => US
[patent_app_date] => 2005-02-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
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[patent_no_of_words] => 4992
[patent_no_of_claims] => 17
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0174/20050174838.pdf
[firstpage_image] =>[orig_patent_app_number] => 11051471
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/051471 | MRAM memory cell having a weak intrinsic anisotropic storage layer and method of producing the same | Feb 6, 2005 | Abandoned |
Array
(
[id] => 670072
[patent_doc_number] => 07095652
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-08-22
[patent_title] => 'Semiconductor storage device'
[patent_app_type] => utility
[patent_app_number] => 11/049727
[patent_app_country] => US
[patent_app_date] => 2005-02-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
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[patent_no_of_words] => 6205
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/095/07095652.pdf
[firstpage_image] =>[orig_patent_app_number] => 11049727
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/049727 | Semiconductor storage device | Feb 3, 2005 | Issued |
Array
(
[id] => 636002
[patent_doc_number] => 07130233
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-10-31
[patent_title] => 'Sensing circuit for single bit-line semiconductor memory device'
[patent_app_type] => utility
[patent_app_number] => 10/906069
[patent_app_country] => US
[patent_app_date] => 2005-02-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
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[patent_no_of_words] => 6164
[patent_no_of_claims] => 14
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/130/07130233.pdf
[firstpage_image] =>[orig_patent_app_number] => 10906069
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/906069 | Sensing circuit for single bit-line semiconductor memory device | Jan 31, 2005 | Issued |
Array
(
[id] => 545039
[patent_doc_number] => 07173848
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-02-06
[patent_title] => 'Magnetic random access memory with memory cell stacks having more than two magnetic states'
[patent_app_type] => utility
[patent_app_number] => 11/048377
[patent_app_country] => US
[patent_app_date] => 2005-02-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
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[patent_no_of_words] => 5587
[patent_no_of_claims] => 21
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/173/07173848.pdf
[firstpage_image] =>[orig_patent_app_number] => 11048377
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/048377 | Magnetic random access memory with memory cell stacks having more than two magnetic states | Jan 31, 2005 | Issued |
Array
(
[id] => 5665893
[patent_doc_number] => 20060171243
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-08-03
[patent_title] => 'MEMORY ARRAY CIRCUIT WITH WORD LINE TIMING CONTROL FOR READ OPERATIONS AND WRITE OPERATIONS'
[patent_app_type] => utility
[patent_app_number] => 10/906037
[patent_app_country] => US
[patent_app_date] => 2005-01-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 2327
[patent_no_of_claims] => 18
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[pdf_file] => publications/A1/0171/20060171243.pdf
[firstpage_image] =>[orig_patent_app_number] => 10906037
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/906037 | MEMORY ARRAY CIRCUIT WITH WORD LINE TIMING CONTROL FOR READ OPERATIONS AND WRITE OPERATIONS | Jan 30, 2005 | Abandoned |
Array
(
[id] => 7003748
[patent_doc_number] => 20050169061
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-08-04
[patent_title] => 'Multi-port memory device for buffering between hosts and non-volatile memory devices'
[patent_app_type] => utility
[patent_app_number] => 11/046407
[patent_app_country] => US
[patent_app_date] => 2005-01-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
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[patent_no_of_words] => 8946
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[pdf_file] => publications/A1/0169/20050169061.pdf
[firstpage_image] =>[orig_patent_app_number] => 11046407
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/046407 | Multi-port memory device for buffering between hosts | Jan 27, 2005 | Issued |
Array
(
[id] => 5874554
[patent_doc_number] => 20060166455
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-07-27
[patent_title] => 'Multilevel programming of phase change memory cells'
[patent_app_type] => utility
[patent_app_number] => 11/042757
[patent_app_country] => US
[patent_app_date] => 2005-01-25
[patent_effective_date] => 0000-00-00
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[pdf_file] => publications/A1/0166/20060166455.pdf
[firstpage_image] =>[orig_patent_app_number] => 11042757
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/042757 | Multilevel programming of phase change memory cells | Jan 24, 2005 | Issued |
Array
(
[id] => 7245354
[patent_doc_number] => 20050141272
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-06-30
[patent_title] => 'Non-volatile memory device and drive method thereof'
[patent_app_type] => utility
[patent_app_number] => 11/024468
[patent_app_country] => US
[patent_app_date] => 2004-12-30
[patent_effective_date] => 0000-00-00
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[pdf_file] => publications/A1/0141/20050141272.pdf
[firstpage_image] =>[orig_patent_app_number] => 11024468
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/024468 | Non-volatile memory device and drive method thereof | Dec 29, 2004 | Issued |
Array
(
[id] => 614182
[patent_doc_number] => 07149137
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-12-12
[patent_title] => 'Process monitoring for ferroelectric memory devices with in-line retention test'
[patent_app_type] => utility
[patent_app_number] => 11/027221
[patent_app_country] => US
[patent_app_date] => 2004-12-30
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/07/149/07149137.pdf
[firstpage_image] =>[orig_patent_app_number] => 11027221
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/027221 | Process monitoring for ferroelectric memory devices with in-line retention test | Dec 29, 2004 | Issued |
Array
(
[id] => 547344
[patent_doc_number] => 07177185
[patent_country] => US
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[patent_issue_date] => 2007-02-13
[patent_title] => 'Non-volatile flash memory device having dual-bit floating gate'
[patent_app_type] => utility
[patent_app_number] => 11/023425
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[pdf_file] => patents/07/177/07177185.pdf
[firstpage_image] =>[orig_patent_app_number] => 11023425
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/023425 | Non-volatile flash memory device having dual-bit floating gate | Dec 28, 2004 | Issued |
Array
(
[id] => 6937705
[patent_doc_number] => 20050111266
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-05-26
[patent_title] => 'Memory device having data paths with multiple speeds'
[patent_app_type] => utility
[patent_app_number] => 11/024200
[patent_app_country] => US
[patent_app_date] => 2004-12-28
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[pdf_file] => publications/A1/0111/20050111266.pdf
[firstpage_image] =>[orig_patent_app_number] => 11024200
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/024200 | Memory device having data paths with multiple speeds | Dec 27, 2004 | Issued |
Array
(
[id] => 7245330
[patent_doc_number] => 20050141266
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[patent_title] => 'Semiconductor device'
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[patent_app_number] => 11/022684
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[firstpage_image] =>[orig_patent_app_number] => 11022684
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/022684 | Semiconductor device | Dec 27, 2004 | Abandoned |
Array
(
[id] => 657259
[patent_doc_number] => 07110293
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-09-19
[patent_title] => 'Non-volatile memory element with oxide stack and non-volatile SRAM using the same'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/022621 | Non-volatile memory element with oxide stack and non-volatile SRAM using the same | Dec 26, 2004 | Issued |
Array
(
[id] => 7054959
[patent_doc_number] => 20050276131
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-12-15
[patent_title] => 'Semiconductor memory device and burn-in test method therefor'
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[firstpage_image] =>[orig_patent_app_number] => 11020323
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/020323 | Semiconductor memory device and burn-in test method therefor | Dec 26, 2004 | Abandoned |
Array
(
[id] => 811810
[patent_doc_number] => 07417907
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2008-08-26
[patent_title] => 'Systems and methods for resolving memory address collisions'
[patent_app_type] => utility
[patent_app_number] => 11/021497
[patent_app_country] => US
[patent_app_date] => 2004-12-23
[patent_effective_date] => 0000-00-00
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/417/07417907.pdf
[firstpage_image] =>[orig_patent_app_number] => 11021497
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/021497 | Systems and methods for resolving memory address collisions | Dec 22, 2004 | Issued |