
Alexander Sofocleous
Examiner (ID: 721)
| Most Active Art Unit | 2824 |
| Art Unit(s) | 2825, 2824, 2895 |
| Total Applications | 473 |
| Issued Applications | 387 |
| Pending Applications | 11 |
| Abandoned Applications | 76 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 7038092
[patent_doc_number] => 20050157526
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-07-21
[patent_title] => 'Semiconductor device'
[patent_app_type] => utility
[patent_app_number] => 11/019321
[patent_app_country] => US
[patent_app_date] => 2004-12-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 30
[patent_figures_cnt] => 30
[patent_no_of_words] => 18000
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0157/20050157526.pdf
[firstpage_image] =>[orig_patent_app_number] => 11019321
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/019321 | Content addressable memory including main-match lines and sub-match lines | Dec 22, 2004 | Issued |
Array
(
[id] => 5893684
[patent_doc_number] => 20060002222
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-01-05
[patent_title] => 'Input/output circuit'
[patent_app_type] => utility
[patent_app_number] => 11/022119
[patent_app_country] => US
[patent_app_date] => 2004-12-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 13
[patent_no_of_words] => 4960
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0002/20060002222.pdf
[firstpage_image] =>[orig_patent_app_number] => 11022119
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/022119 | Input/output circuit | Dec 22, 2004 | Issued |
Array
(
[id] => 5654248
[patent_doc_number] => 20060139983
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-06-29
[patent_title] => 'Memory module routing'
[patent_app_type] => utility
[patent_app_number] => 11/021611
[patent_app_country] => US
[patent_app_date] => 2004-12-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 5541
[patent_no_of_claims] => 55
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0139/20060139983.pdf
[firstpage_image] =>[orig_patent_app_number] => 11021611
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/021611 | Memory module routing | Dec 22, 2004 | Abandoned |
Array
(
[id] => 7189086
[patent_doc_number] => 20050162945
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-07-28
[patent_title] => 'Semiconductor memory device having repair circuit'
[patent_app_type] => utility
[patent_app_number] => 11/015419
[patent_app_country] => US
[patent_app_date] => 2004-12-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 3846
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0162/20050162945.pdf
[firstpage_image] =>[orig_patent_app_number] => 11015419
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/015419 | Semiconductor memory device having repair circuit | Dec 19, 2004 | Issued |
Array
(
[id] => 714049
[patent_doc_number] => 07057964
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-06-06
[patent_title] => 'Semiconductor memory device with efficient multiplexing of I/O pad in multi-chip package'
[patent_app_type] => utility
[patent_app_number] => 11/015421
[patent_app_country] => US
[patent_app_date] => 2004-12-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 3
[patent_no_of_words] => 2695
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 172
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/057/07057964.pdf
[firstpage_image] =>[orig_patent_app_number] => 11015421
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/015421 | Semiconductor memory device with efficient multiplexing of I/O pad in multi-chip package | Dec 19, 2004 | Issued |
Array
(
[id] => 6995386
[patent_doc_number] => 20050135164
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-06-23
[patent_title] => 'Semiconductor memory device which compensates for delay time variations of multi-bit data'
[patent_app_type] => utility
[patent_app_number] => 11/010325
[patent_app_country] => US
[patent_app_date] => 2004-12-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 4891
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0135/20050135164.pdf
[firstpage_image] =>[orig_patent_app_number] => 11010325
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/010325 | Semiconductor memory device which compensates for delay time variations of multi-bit data | Dec 13, 2004 | Issued |
Array
(
[id] => 628405
[patent_doc_number] => 07136314
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-11-14
[patent_title] => 'Memory device and test method thereof'
[patent_app_type] => utility
[patent_app_number] => 11/008273
[patent_app_country] => US
[patent_app_date] => 2004-12-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 1975
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 155
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/136/07136314.pdf
[firstpage_image] =>[orig_patent_app_number] => 11008273
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/008273 | Memory device and test method thereof | Dec 9, 2004 | Issued |
Array
(
[id] => 5792372
[patent_doc_number] => 20060013053
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-01-19
[patent_title] => 'Semiconductor memory device for performing refresh operation'
[patent_app_type] => utility
[patent_app_number] => 11/008279
[patent_app_country] => US
[patent_app_date] => 2004-12-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 3511
[patent_no_of_claims] => 10
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0013/20060013053.pdf
[firstpage_image] =>[orig_patent_app_number] => 11008279
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/008279 | Semiconductor memory device for performing refresh operation | Dec 9, 2004 | Issued |
Array
(
[id] => 553935
[patent_doc_number] => 07164600
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-01-16
[patent_title] => 'Reducing DQ pin capacitance in a memory device'
[patent_app_type] => utility
[patent_app_number] => 11/010235
[patent_app_country] => US
[patent_app_date] => 2004-12-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
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[patent_no_of_words] => 6221
[patent_no_of_claims] => 14
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[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/164/07164600.pdf
[firstpage_image] =>[orig_patent_app_number] => 11010235
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/010235 | Reducing DQ pin capacitance in a memory device | Dec 9, 2004 | Issued |
Array
(
[id] => 682502
[patent_doc_number] => 07085167
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-08-01
[patent_title] => 'Methods for programming user data and confirmation information in nonvolatile memory devices'
[patent_app_type] => utility
[patent_app_number] => 11/009125
[patent_app_country] => US
[patent_app_date] => 2004-12-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 6
[patent_no_of_words] => 5722
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 1
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[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/085/07085167.pdf
[firstpage_image] =>[orig_patent_app_number] => 11009125
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/009125 | Methods for programming user data and confirmation information in nonvolatile memory devices | Dec 9, 2004 | Issued |
Array
(
[id] => 7172554
[patent_doc_number] => 20050122818
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-06-09
[patent_title] => 'Ferro electric memory device and electronic device'
[patent_app_type] => utility
[patent_app_number] => 10/980979
[patent_app_country] => US
[patent_app_date] => 2004-11-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
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[patent_no_of_words] => 3499
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0122/20050122818.pdf
[firstpage_image] =>[orig_patent_app_number] => 10980979
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/980979 | Ferroelectric memory device and electronic device | Nov 3, 2004 | Issued |
Array
(
[id] => 631898
[patent_doc_number] => 07133320
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-11-07
[patent_title] => 'Flood mode implementation for continuous bitline local evaluation circuit'
[patent_app_type] => utility
[patent_app_number] => 10/981153
[patent_app_country] => US
[patent_app_date] => 2004-11-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/133/07133320.pdf
[firstpage_image] =>[orig_patent_app_number] => 10981153
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/981153 | Flood mode implementation for continuous bitline local evaluation circuit | Nov 3, 2004 | Issued |
Array
(
[id] => 5806342
[patent_doc_number] => 20060092695
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-05-04
[patent_title] => 'Hybrid memory array with single cycle access'
[patent_app_type] => utility
[patent_app_number] => 10/979839
[patent_app_country] => US
[patent_app_date] => 2004-11-02
[patent_effective_date] => 0000-00-00
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[pdf_file] => publications/A1/0092/20060092695.pdf
[firstpage_image] =>[orig_patent_app_number] => 10979839
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/979839 | Hybrid memory array with single cycle access | Nov 1, 2004 | Abandoned |
Array
(
[id] => 728080
[patent_doc_number] => 07046539
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2006-05-16
[patent_title] => 'Mechanical memory'
[patent_app_type] => utility
[patent_app_number] => 10/979419
[patent_app_country] => US
[patent_app_date] => 2004-11-02
[patent_effective_date] => 0000-00-00
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/046/07046539.pdf
[firstpage_image] =>[orig_patent_app_number] => 10979419
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/979419 | Mechanical memory | Nov 1, 2004 | Issued |
Array
(
[id] => 916553
[patent_doc_number] => 07327613
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-02-05
[patent_title] => 'Input circuit for a memory device'
[patent_app_type] => utility
[patent_app_number] => 10/965461
[patent_app_country] => US
[patent_app_date] => 2004-10-14
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/327/07327613.pdf
[firstpage_image] =>[orig_patent_app_number] => 10965461
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/965461 | Input circuit for a memory device | Oct 13, 2004 | Issued |
Array
(
[id] => 5764017
[patent_doc_number] => 20060017719
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-01-26
[patent_title] => 'Apparatus and method of driving memory for display device'
[patent_app_type] => utility
[patent_app_number] => 10/960859
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[patent_effective_date] => 0000-00-00
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[pdf_file] => publications/A1/0017/20060017719.pdf
[firstpage_image] =>[orig_patent_app_number] => 10960859
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/960859 | Apparatus and method of driving memory for display device | Oct 6, 2004 | Issued |
Array
(
[id] => 589201
[patent_doc_number] => 07453741
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-11-18
[patent_title] => 'Semiconductor device card providing multiple working voltages'
[patent_app_type] => utility
[patent_app_number] => 10/960733
[patent_app_country] => US
[patent_app_date] => 2004-10-07
[patent_effective_date] => 0000-00-00
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/453/07453741.pdf
[firstpage_image] =>[orig_patent_app_number] => 10960733
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/960733 | Semiconductor device card providing multiple working voltages | Oct 6, 2004 | Issued |
Array
(
[id] => 5076985
[patent_doc_number] => 20070120209
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-05-31
[patent_title] => 'Magnetic field shaping conductor'
[patent_app_type] => utility
[patent_app_number] => 10/574365
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[patent_app_date] => 2004-10-01
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[pdf_file] => publications/A1/0120/20070120209.pdf
[firstpage_image] =>[orig_patent_app_number] => 10574365
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/574365 | Magnetic field shaping conductor | Sep 30, 2004 | Issued |
Array
(
[id] => 5797830
[patent_doc_number] => 20060034116
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-02-16
[patent_title] => 'Cross point array cell with series connected semiconductor diode and phase change storage media'
[patent_app_type] => utility
[patent_app_number] => 10/918101
[patent_app_country] => US
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0034/20060034116.pdf
[firstpage_image] =>[orig_patent_app_number] => 10918101
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/918101 | Cross point array cell with series connected semiconductor diode and phase change storage media | Aug 12, 2004 | Abandoned |
Array
(
[id] => 854729
[patent_doc_number] => 07379349
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-05-27
[patent_title] => 'Simultaneous and selective memory macro testing'
[patent_app_type] => utility
[patent_app_number] => 10/891041
[patent_app_country] => US
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/379/07379349.pdf
[firstpage_image] =>[orig_patent_app_number] => 10891041
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/891041 | Simultaneous and selective memory macro testing | Jul 14, 2004 | Issued |