Search

Alexander Sofocleous

Examiner (ID: 721)

Most Active Art Unit
2824
Art Unit(s)
2825, 2824, 2895
Total Applications
473
Issued Applications
387
Pending Applications
11
Abandoned Applications
76

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7569191 [patent_doc_number] => 20110289254 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-11-24 [patent_title] => 'CONFIGURABLE DIGITAL AND ANALOG INPUT/OUTPUT INTERFACE IN A MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 13/192948 [patent_app_country] => US [patent_app_date] => 2011-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8408 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0289/20110289254.pdf [firstpage_image] =>[orig_patent_app_number] => 13192948 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/192948
Configurable digital and analog input/output interface in a memory device Jul 27, 2011 Issued
Array ( [id] => 9185414 [patent_doc_number] => 08625360 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-01-07 [patent_title] => 'Semiconductor storage device operative to search for data' [patent_app_type] => utility [patent_app_number] => 13/165457 [patent_app_country] => US [patent_app_date] => 2011-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 31 [patent_no_of_words] => 7250 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 266 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13165457 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/165457
Semiconductor storage device operative to search for data Jun 20, 2011 Issued
Array ( [id] => 8934064 [patent_doc_number] => 08493774 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-07-23 [patent_title] => 'Performing logic functions on more than one memory cell within an array of memory cells' [patent_app_type] => utility [patent_app_number] => 13/162753 [patent_app_country] => US [patent_app_date] => 2011-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7615 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 40 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13162753 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/162753
Performing logic functions on more than one memory cell within an array of memory cells Jun 16, 2011 Issued
Array ( [id] => 7999379 [patent_doc_number] => 08081537 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-12-20 [patent_title] => 'Circuit for providing chip-select signals to a plurality of ranks of a DDR memory module' [patent_app_type] => utility [patent_app_number] => 13/154172 [patent_app_country] => US [patent_app_date] => 2011-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 25 [patent_no_of_words] => 16047 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/081/08081537.pdf [firstpage_image] =>[orig_patent_app_number] => 13154172 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/154172
Circuit for providing chip-select signals to a plurality of ranks of a DDR memory module Jun 5, 2011 Issued
Array ( [id] => 8068241 [patent_doc_number] => 20110242902 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-10-06 [patent_title] => 'NONVOLATILE SEMICONDUCTOR MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 13/073365 [patent_app_country] => US [patent_app_date] => 2011-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6365 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0242/20110242902.pdf [firstpage_image] =>[orig_patent_app_number] => 13073365 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/073365
NONVOLATILE SEMICONDUCTOR MEMORY DEVICE Mar 27, 2011 Abandoned
Array ( [id] => 9168208 [patent_doc_number] => 08593892 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-11-26 [patent_title] => 'Semiconductor device and system' [patent_app_type] => utility [patent_app_number] => 13/035103 [patent_app_country] => US [patent_app_date] => 2011-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 18 [patent_no_of_words] => 6881 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13035103 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/035103
Semiconductor device and system Feb 24, 2011 Issued
Array ( [id] => 6078120 [patent_doc_number] => 20110141789 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-06-16 [patent_title] => 'MEMORY MODULE AND MEMORY SYSTEM' [patent_app_type] => utility [patent_app_number] => 13/033424 [patent_app_country] => US [patent_app_date] => 2011-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 41 [patent_figures_cnt] => 41 [patent_no_of_words] => 15537 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0141/20110141789.pdf [firstpage_image] =>[orig_patent_app_number] => 13033424 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/033424
Memory module and memory system Feb 22, 2011 Issued
Array ( [id] => 7999377 [patent_doc_number] => 08081536 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-12-20 [patent_title] => 'Circuit for memory module' [patent_app_type] => utility [patent_app_number] => 13/032470 [patent_app_country] => US [patent_app_date] => 2011-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 34 [patent_no_of_words] => 20602 [patent_no_of_claims] => 42 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 207 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/081/08081536.pdf [firstpage_image] =>[orig_patent_app_number] => 13032470 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/032470
Circuit for memory module Feb 21, 2011 Issued
Array ( [id] => 6078126 [patent_doc_number] => 20110141795 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-06-16 [patent_title] => 'MULTI-PORT MEMORY BASED ON DRAM CORE' [patent_app_type] => utility [patent_app_number] => 13/031080 [patent_app_country] => US [patent_app_date] => 2011-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 148 [patent_figures_cnt] => 148 [patent_no_of_words] => 51713 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13031080 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/031080
Multi-port memory based on DRAM core Feb 17, 2011 Issued
Array ( [id] => 6060638 [patent_doc_number] => 20110199822 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-08-18 [patent_title] => 'METHOD AND APPARATUS FOR CONTROLLING PAGE BUFFER OF NON-VOLATILE MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 13/028313 [patent_app_country] => US [patent_app_date] => 2011-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3591 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0199/20110199822.pdf [firstpage_image] =>[orig_patent_app_number] => 13028313 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/028313
Method and apparatus for controlling page buffer of non-volatile memory device Feb 15, 2011 Issued
Array ( [id] => 8307197 [patent_doc_number] => 08228743 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-07-24 [patent_title] => 'Memory cells containing charge-trapping zones' [patent_app_type] => utility [patent_app_number] => 13/024903 [patent_app_country] => US [patent_app_date] => 2011-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 19 [patent_no_of_words] => 9351 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13024903 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/024903
Memory cells containing charge-trapping zones Feb 9, 2011 Issued
Array ( [id] => 6181070 [patent_doc_number] => 20110122710 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-05-26 [patent_title] => 'METHOD AND APPARATUS FOR GENERATING A SEQUENCE OF CLOCK SIGNALS' [patent_app_type] => utility [patent_app_number] => 13/021223 [patent_app_country] => US [patent_app_date] => 2011-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5885 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0122/20110122710.pdf [firstpage_image] =>[orig_patent_app_number] => 13021223 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/021223
Method and apparatus for generating a sequence of clock signals Feb 3, 2011 Issued
Array ( [id] => 9087772 [patent_doc_number] => 08559207 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-10-15 [patent_title] => 'Variable resistance memory device with trigger circuit for set/reset write operations' [patent_app_type] => utility [patent_app_number] => 13/009077 [patent_app_country] => US [patent_app_date] => 2011-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 26 [patent_no_of_words] => 7913 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13009077 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/009077
Variable resistance memory device with trigger circuit for set/reset write operations Jan 18, 2011 Issued
Array ( [id] => 6057228 [patent_doc_number] => 20110113168 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-05-12 [patent_title] => 'Methods of Communicating Data Using Inversion and Related Systems' [patent_app_type] => utility [patent_app_number] => 13/008340 [patent_app_country] => US [patent_app_date] => 2011-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 12706 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0113/20110113168.pdf [firstpage_image] =>[orig_patent_app_number] => 13008340 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/008340
Methods of Communicating Data Using Inversion and Related Systems Jan 17, 2011 Abandoned
Array ( [id] => 7980167 [patent_doc_number] => 08072837 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-12-06 [patent_title] => 'Circuit providing load isolation and memory domain translation for memory module' [patent_app_type] => utility [patent_app_number] => 12/981380 [patent_app_country] => US [patent_app_date] => 2010-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 34 [patent_no_of_words] => 20127 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 292 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/072/08072837.pdf [firstpage_image] =>[orig_patent_app_number] => 12981380 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/981380
Circuit providing load isolation and memory domain translation for memory module Dec 28, 2010 Issued
Array ( [id] => 7980167 [patent_doc_number] => 08072837 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-12-06 [patent_title] => 'Circuit providing load isolation and memory domain translation for memory module' [patent_app_type] => utility [patent_app_number] => 12/981380 [patent_app_country] => US [patent_app_date] => 2010-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 34 [patent_no_of_words] => 20127 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 292 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/072/08072837.pdf [firstpage_image] =>[orig_patent_app_number] => 12981380 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/981380
Circuit providing load isolation and memory domain translation for memory module Dec 28, 2010 Issued
Array ( [id] => 7980167 [patent_doc_number] => 08072837 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-12-06 [patent_title] => 'Circuit providing load isolation and memory domain translation for memory module' [patent_app_type] => utility [patent_app_number] => 12/981380 [patent_app_country] => US [patent_app_date] => 2010-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 34 [patent_no_of_words] => 20127 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 292 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/072/08072837.pdf [firstpage_image] =>[orig_patent_app_number] => 12981380 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/981380
Circuit providing load isolation and memory domain translation for memory module Dec 28, 2010 Issued
Array ( [id] => 7980167 [patent_doc_number] => 08072837 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-12-06 [patent_title] => 'Circuit providing load isolation and memory domain translation for memory module' [patent_app_type] => utility [patent_app_number] => 12/981380 [patent_app_country] => US [patent_app_date] => 2010-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 34 [patent_no_of_words] => 20127 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 292 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/072/08072837.pdf [firstpage_image] =>[orig_patent_app_number] => 12981380 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/981380
Circuit providing load isolation and memory domain translation for memory module Dec 28, 2010 Issued
Array ( [id] => 5934667 [patent_doc_number] => 20110211392 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-09-01 [patent_title] => 'CELL STRING OF A MEMORY CELL ARRAY AND METHOD OF ERASING THE SAME' [patent_app_type] => utility [patent_app_number] => 12/961647 [patent_app_country] => US [patent_app_date] => 2010-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 10590 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0211/20110211392.pdf [firstpage_image] =>[orig_patent_app_number] => 12961647 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/961647
CELL STRING OF A MEMORY CELL ARRAY AND METHOD OF ERASING THE SAME Dec 6, 2010 Abandoned
Array ( [id] => 6123495 [patent_doc_number] => 20110085406 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-04-14 [patent_title] => 'CIRCUIT PROVIDING LOAD ISOLATION AND MEMORY DOMAIN TRANSLATION FOR MEMORY MODULE' [patent_app_type] => utility [patent_app_number] => 12/955711 [patent_app_country] => US [patent_app_date] => 2010-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 20121 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0085/20110085406.pdf [firstpage_image] =>[orig_patent_app_number] => 12955711 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/955711
Circuit providing load isolation and memory domain translation for memory module Nov 28, 2010 Issued
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