
Alexander Sofocleous
Examiner (ID: 721)
| Most Active Art Unit | 2824 |
| Art Unit(s) | 2825, 2824, 2895 |
| Total Applications | 473 |
| Issued Applications | 387 |
| Pending Applications | 11 |
| Abandoned Applications | 76 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 4452963
[patent_doc_number] => 07965578
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-06-21
[patent_title] => 'Circuit for providing chip-select signals to a plurality of ranks of a DDR memory module'
[patent_app_type] => utility
[patent_app_number] => 12/954492
[patent_app_country] => US
[patent_app_date] => 2010-11-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
[patent_figures_cnt] => 25
[patent_no_of_words] => 16022
[patent_no_of_claims] => 31
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 322
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/965/07965578.pdf
[firstpage_image] =>[orig_patent_app_number] => 12954492
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/954492 | Circuit for providing chip-select signals to a plurality of ranks of a DDR memory module | Nov 23, 2010 | Issued |
Array
(
[id] => 4452963
[patent_doc_number] => 07965578
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-06-21
[patent_title] => 'Circuit for providing chip-select signals to a plurality of ranks of a DDR memory module'
[patent_app_type] => utility
[patent_app_number] => 12/954492
[patent_app_country] => US
[patent_app_date] => 2010-11-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
[patent_figures_cnt] => 25
[patent_no_of_words] => 16022
[patent_no_of_claims] => 31
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 322
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/965/07965578.pdf
[firstpage_image] =>[orig_patent_app_number] => 12954492
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/954492 | Circuit for providing chip-select signals to a plurality of ranks of a DDR memory module | Nov 23, 2010 | Issued |
Array
(
[id] => 4452963
[patent_doc_number] => 07965578
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-06-21
[patent_title] => 'Circuit for providing chip-select signals to a plurality of ranks of a DDR memory module'
[patent_app_type] => utility
[patent_app_number] => 12/954492
[patent_app_country] => US
[patent_app_date] => 2010-11-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
[patent_figures_cnt] => 25
[patent_no_of_words] => 16022
[patent_no_of_claims] => 31
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 322
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/965/07965578.pdf
[firstpage_image] =>[orig_patent_app_number] => 12954492
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/954492 | Circuit for providing chip-select signals to a plurality of ranks of a DDR memory module | Nov 23, 2010 | Issued |
Array
(
[id] => 4452963
[patent_doc_number] => 07965578
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-06-21
[patent_title] => 'Circuit for providing chip-select signals to a plurality of ranks of a DDR memory module'
[patent_app_type] => utility
[patent_app_number] => 12/954492
[patent_app_country] => US
[patent_app_date] => 2010-11-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
[patent_figures_cnt] => 25
[patent_no_of_words] => 16022
[patent_no_of_claims] => 31
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 322
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/965/07965578.pdf
[firstpage_image] =>[orig_patent_app_number] => 12954492
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/954492 | Circuit for providing chip-select signals to a plurality of ranks of a DDR memory module | Nov 23, 2010 | Issued |
Array
(
[id] => 4630577
[patent_doc_number] => 08009482
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-08-30
[patent_title] => 'High temperature methods for enhancing retention characteristics of memory devices'
[patent_app_type] => utility
[patent_app_number] => 12/911264
[patent_app_country] => US
[patent_app_date] => 2010-10-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 4828
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 125
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/08/009/08009482.pdf
[firstpage_image] =>[orig_patent_app_number] => 12911264
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/911264 | High temperature methods for enhancing retention characteristics of memory devices | Oct 24, 2010 | Issued |
Array
(
[id] => 7556469
[patent_doc_number] => 08068373
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2011-11-29
[patent_title] => 'Power management of memory via wake/sleep cycles'
[patent_app_type] => utility
[patent_app_number] => 12/911181
[patent_app_country] => US
[patent_app_date] => 2010-10-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 4865
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 121
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/08/068/08068373.pdf
[firstpage_image] =>[orig_patent_app_number] => 12911181
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/911181 | Power management of memory via wake/sleep cycles | Oct 24, 2010 | Issued |
Array
(
[id] => 5949586
[patent_doc_number] => 20110032025
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2011-02-10
[patent_title] => 'PROGRAMMABLE SEMICONDUCTOR DEVICE'
[patent_app_type] => utility
[patent_app_number] => 12/911379
[patent_app_country] => US
[patent_app_date] => 2010-10-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 16
[patent_no_of_words] => 3031
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0032/20110032025.pdf
[firstpage_image] =>[orig_patent_app_number] => 12911379
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/911379 | Programmable semiconductor device | Oct 24, 2010 | Issued |
Array
(
[id] => 8365084
[patent_doc_number] => 08254154
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2012-08-28
[patent_title] => 'NAND flash memory having bit line with smaller width than width of peripheral interconnect line'
[patent_app_type] => utility
[patent_app_number] => 12/923309
[patent_app_country] => US
[patent_app_date] => 2010-09-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 20
[patent_no_of_words] => 2804
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 111
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12923309
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/923309 | NAND flash memory having bit line with smaller width than width of peripheral interconnect line | Sep 13, 2010 | Issued |
Array
(
[id] => 6571406
[patent_doc_number] => 20100290293
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-11-18
[patent_title] => 'METHOD OF IDENTIFYING LOGICAL INFORMATION IN A PROGRAMMING AND ERASING CELL BY ON-SIDE READING SCHEME'
[patent_app_type] => utility
[patent_app_number] => 12/845064
[patent_app_country] => US
[patent_app_date] => 2010-07-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 3605
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0290/20100290293.pdf
[firstpage_image] =>[orig_patent_app_number] => 12845064
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/845064 | METHOD OF IDENTIFYING LOGICAL INFORMATION IN A PROGRAMMING AND ERASING CELL BY ON-SIDE READING SCHEME | Jul 27, 2010 | Abandoned |
Array
(
[id] => 7541625
[patent_doc_number] => 08059473
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-11-15
[patent_title] => 'Non-volatile memory device'
[patent_app_type] => utility
[patent_app_number] => 12/844234
[patent_app_country] => US
[patent_app_date] => 2010-07-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 35
[patent_no_of_words] => 6445
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 175
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/08/059/08059473.pdf
[firstpage_image] =>[orig_patent_app_number] => 12844234
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/844234 | Non-volatile memory device | Jul 26, 2010 | Issued |
Array
(
[id] => 7980165
[patent_doc_number] => 08072836
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-12-06
[patent_title] => 'Systems, methods and devices for arbitrating die stack position in a multi-die stack device'
[patent_app_type] => utility
[patent_app_number] => 12/829949
[patent_app_country] => US
[patent_app_date] => 2010-07-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 5
[patent_no_of_words] => 4439
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 105
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/08/072/08072836.pdf
[firstpage_image] =>[orig_patent_app_number] => 12829949
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/829949 | Systems, methods and devices for arbitrating die stack position in a multi-die stack device | Jul 1, 2010 | Issued |
Array
(
[id] => 9312450
[patent_doc_number] => 08653672
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2014-02-18
[patent_title] => 'Three dimensional structure memory'
[patent_app_type] => utility
[patent_app_number] => 12/788618
[patent_app_country] => US
[patent_app_date] => 2010-05-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 7187
[patent_no_of_claims] => 169
[patent_no_of_ind_claims] => 8
[patent_words_short_claim] => 47
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12788618
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/788618 | Three dimensional structure memory | May 26, 2010 | Issued |
Array
(
[id] => 7560089
[patent_doc_number] => 20110273921
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2011-11-10
[patent_title] => 'INTEGRATABLE PROGRAMMABLE CAPACITIVE DEVICE'
[patent_app_type] => utility
[patent_app_number] => 12/775237
[patent_app_country] => US
[patent_app_date] => 2010-05-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 4553
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0273/20110273921.pdf
[firstpage_image] =>[orig_patent_app_number] => 12775237
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/775237 | Integratable programmable capacitive device | May 5, 2010 | Issued |
Array
(
[id] => 7541604
[patent_doc_number] => 08059452
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-11-15
[patent_title] => 'Cell structure for dual port SRAM'
[patent_app_type] => utility
[patent_app_number] => 12/773662
[patent_app_country] => US
[patent_app_date] => 2010-05-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 3068
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 113
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/08/059/08059452.pdf
[firstpage_image] =>[orig_patent_app_number] => 12773662
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/773662 | Cell structure for dual port SRAM | May 3, 2010 | Issued |
Array
(
[id] => 6289661
[patent_doc_number] => 20100238754
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-09-23
[patent_title] => 'CLOCK AND POWER FAULT DETECTION FOR MEMORY MODULES'
[patent_app_type] => utility
[patent_app_number] => 12/770610
[patent_app_country] => US
[patent_app_date] => 2010-04-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 16
[patent_no_of_words] => 5290
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0238/20100238754.pdf
[firstpage_image] =>[orig_patent_app_number] => 12770610
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/770610 | Clock and power fault detection for memory modules | Apr 28, 2010 | Issued |
Array
(
[id] => 9287764
[patent_doc_number] => 08644105
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2014-02-04
[patent_title] => 'Clock and power fault detection for memory modules'
[patent_app_type] => utility
[patent_app_number] => 12/770576
[patent_app_country] => US
[patent_app_date] => 2010-04-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 15
[patent_no_of_words] => 5291
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 7
[patent_words_short_claim] => 109
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12770576
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/770576 | Clock and power fault detection for memory modules | Apr 28, 2010 | Issued |
Array
(
[id] => 8556674
[patent_doc_number] => 08331152
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2012-12-11
[patent_title] => 'Nonvolatile memory device'
[patent_app_type] => utility
[patent_app_number] => 12/765411
[patent_app_country] => US
[patent_app_date] => 2010-04-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 17
[patent_no_of_words] => 8482
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 172
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12765411
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/765411 | Nonvolatile memory device | Apr 21, 2010 | Issued |
Array
(
[id] => 8550054
[patent_doc_number] => 08324940
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2012-12-04
[patent_title] => 'Nanowire circuits in matched devices'
[patent_app_type] => utility
[patent_app_number] => 12/758939
[patent_app_country] => US
[patent_app_date] => 2010-04-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 4
[patent_no_of_words] => 2385
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 52
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12758939
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/758939 | Nanowire circuits in matched devices | Apr 12, 2010 | Issued |
Array
(
[id] => 7765440
[patent_doc_number] => 08116119
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2012-02-14
[patent_title] => 'Desensitizing static random access memory (SRAM) to process variations'
[patent_app_type] => utility
[patent_app_number] => 12/758579
[patent_app_country] => US
[patent_app_date] => 2010-04-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 5229
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 124
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/08/116/08116119.pdf
[firstpage_image] =>[orig_patent_app_number] => 12758579
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/758579 | Desensitizing static random access memory (SRAM) to process variations | Apr 11, 2010 | Issued |
Array
(
[id] => 7773019
[patent_doc_number] => 20120037939
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-02-16
[patent_title] => 'LIGHT EMITTING DIODE'
[patent_app_type] => utility
[patent_app_number] => 13/264004
[patent_app_country] => US
[patent_app_date] => 2010-04-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 6306
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0037/20120037939.pdf
[firstpage_image] =>[orig_patent_app_number] => 13264004
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/264004 | LIGHT EMITTING DIODE | Apr 11, 2010 | Abandoned |