
Alexander Sofocleous
Examiner (ID: 721)
| Most Active Art Unit | 2824 |
| Art Unit(s) | 2825, 2824, 2895 |
| Total Applications | 473 |
| Issued Applications | 387 |
| Pending Applications | 11 |
| Abandoned Applications | 76 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 8167419
[patent_doc_number] => 08174888
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2012-05-08
[patent_title] => 'Page-buffer and non-volatile semiconductor memory including page buffer'
[patent_app_type] => utility
[patent_app_number] => 12/752213
[patent_app_country] => US
[patent_app_date] => 2010-04-01
[patent_effective_date] => 0000-00-00
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[patent_figures_cnt] => 24
[patent_no_of_words] => 15848
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/08/174/08174888.pdf
[firstpage_image] =>[orig_patent_app_number] => 12752213
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/752213 | Page-buffer and non-volatile semiconductor memory including page buffer | Mar 31, 2010 | Issued |
Array
(
[id] => 8529238
[patent_doc_number] => 08305819
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2012-11-06
[patent_title] => 'Data output circuit of semiconductor memory device'
[patent_app_type] => utility
[patent_app_number] => 12/751425
[patent_app_country] => US
[patent_app_date] => 2010-03-31
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[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12751425
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/751425 | Data output circuit of semiconductor memory device | Mar 30, 2010 | Issued |
Array
(
[id] => 8436828
[patent_doc_number] => 08284603
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2012-10-09
[patent_title] => 'Memory devices and operations thereof using program state determination based on data value distribution'
[patent_app_type] => utility
[patent_app_number] => 12/748113
[patent_app_country] => US
[patent_app_date] => 2010-03-26
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[patent_drawing_sheets_cnt] => 14
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[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12748113
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/748113 | Memory devices and operations thereof using program state determination based on data value distribution | Mar 25, 2010 | Issued |
Array
(
[id] => 6227622
[patent_doc_number] => 20100182822
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-07-22
[patent_title] => 'DEVICE AND METHOD FOR USING DYNAMIC CELL PLATE SENSING IN A DRAM MEMORY CELL'
[patent_app_type] => utility
[patent_app_number] => 12/729820
[patent_app_country] => US
[patent_app_date] => 2010-03-23
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[pdf_file] => publications/A1/0182/20100182822.pdf
[firstpage_image] =>[orig_patent_app_number] => 12729820
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/729820 | Device and method for using dynamic cell plate sensing in a DRAM memory cell | Mar 22, 2010 | Issued |
Array
(
[id] => 8556707
[patent_doc_number] => 08331185
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2012-12-11
[patent_title] => 'Semiconductor device having electrical fuses with less power consumption and interconnection arrangement'
[patent_app_type] => utility
[patent_app_number] => 12/723218
[patent_app_country] => US
[patent_app_date] => 2010-03-12
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/723218 | Semiconductor device having electrical fuses with less power consumption and interconnection arrangement | Mar 11, 2010 | Issued |
Array
(
[id] => 6013204
[patent_doc_number] => 20110222338
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2011-09-15
[patent_title] => 'METHOD OF HANDLING REFERENCE CELLS IN NVM ARRAYS'
[patent_app_type] => utility
[patent_app_number] => 12/720687
[patent_app_country] => US
[patent_app_date] => 2010-03-10
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[pdf_file] => publications/A1/0222/20110222338.pdf
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/720687 | Method of handling reference cells in NVM arrays | Mar 9, 2010 | Issued |
Array
(
[id] => 8714675
[patent_doc_number] => 08400819
[patent_country] => US
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[patent_issue_date] => 2013-03-19
[patent_title] => 'Integrated circuit having variable memory array power supply voltage'
[patent_app_type] => utility
[patent_app_number] => 12/714079
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[patent_app_date] => 2010-02-26
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/714079 | Integrated circuit having variable memory array power supply voltage | Feb 25, 2010 | Issued |
Array
(
[id] => 4615340
[patent_doc_number] => 07990787
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[patent_issue_date] => 2011-08-02
[patent_title] => 'Memory compiler redundancy'
[patent_app_type] => utility
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[patent_app_country] => US
[patent_app_date] => 2010-02-05
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[firstpage_image] =>[orig_patent_app_number] => 12701519
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/701519 | Memory compiler redundancy | Feb 4, 2010 | Issued |
Array
(
[id] => 6316598
[patent_doc_number] => 20100195413
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-08-05
[patent_title] => 'SEMICONDUCTOR MEMORY DEVICE'
[patent_app_type] => utility
[patent_app_number] => 12/700121
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[firstpage_image] =>[orig_patent_app_number] => 12700121
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/700121 | Mode register output circuit | Feb 3, 2010 | Issued |
Array
(
[id] => 10053284
[patent_doc_number] => 09093163
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[patent_kind] => B2
[patent_issue_date] => 2015-07-28
[patent_title] => 'Magnetoresistive device'
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[patent_app_number] => 12/687550
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/687550 | Magnetoresistive device | Jan 13, 2010 | Issued |
Array
(
[id] => 8341554
[patent_doc_number] => 08243485
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[patent_kind] => B2
[patent_issue_date] => 2012-08-14
[patent_title] => 'Semiconductor apparatus and chip selection method thereof'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/650501 | Semiconductor apparatus and chip selection method thereof | Dec 29, 2009 | Issued |
Array
(
[id] => 8295724
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[patent_title] => 'Semiconductor apparatus and chip selection method thereof'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/650507 | Semiconductor apparatus and chip selection method thereof | Dec 29, 2009 | Issued |
Array
(
[id] => 5966878
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[patent_issue_date] => 2011-06-23
[patent_title] => 'Non-volatile memory cell array'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/655157 | Arrangement of pairs of NAND strings that share bitline contacts while utilizing distinct sources lines | Dec 22, 2009 | Issued |
Array
(
[id] => 6564332
[patent_doc_number] => 20100128507
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[patent_title] => 'CIRCUIT PROVIDING LOAD ISOLATION AND MEMORY DOMAIN TRANSLATION FOR MEMORY MODULE'
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[patent_app_number] => 12/629827
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[firstpage_image] =>[orig_patent_app_number] => 12629827
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/629827 | Circuit providing load isolation and memory domain translation for memory module | Dec 1, 2009 | Issued |
Array
(
[id] => 6361064
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[patent_title] => 'METHOD FOR OPERATING ONE-TIME PROGRAMMABLE READ-ONLY MEMORY'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/627244 | Method for operating one-time programmable read-only memory | Nov 29, 2009 | Issued |
Array
(
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[patent_title] => 'Maintenance operations for multi-level data storage cells'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/624020 | Maintenance operations for multi-level data storage cells | Nov 22, 2009 | Issued |
Array
(
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/619227 | Nonvolatile memory device with incremental step pulse programming | Nov 15, 2009 | Issued |
Array
(
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[patent_title] => 'DATA STATE-DEPENDENT CHANNEL BOOSTING TO REDUCE CHANNEL-TO-FLOATING GATE COUPLING IN MEMORY'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/616269 | Data state-dependent channel boosting to reduce channel-to-floating gate coupling in memory | Nov 10, 2009 | Issued |
Array
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Array
(
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/606871 | Nanowire-based memristor devices | Oct 26, 2009 | Issued |