Search

Alexander Sofocleous

Examiner (ID: 721)

Most Active Art Unit
2824
Art Unit(s)
2825, 2824, 2895
Total Applications
473
Issued Applications
387
Pending Applications
11
Abandoned Applications
76

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 8167419 [patent_doc_number] => 08174888 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-05-08 [patent_title] => 'Page-buffer and non-volatile semiconductor memory including page buffer' [patent_app_type] => utility [patent_app_number] => 12/752213 [patent_app_country] => US [patent_app_date] => 2010-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 24 [patent_no_of_words] => 15848 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/174/08174888.pdf [firstpage_image] =>[orig_patent_app_number] => 12752213 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/752213
Page-buffer and non-volatile semiconductor memory including page buffer Mar 31, 2010 Issued
Array ( [id] => 8529238 [patent_doc_number] => 08305819 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-11-06 [patent_title] => 'Data output circuit of semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 12/751425 [patent_app_country] => US [patent_app_date] => 2010-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 7949 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12751425 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/751425
Data output circuit of semiconductor memory device Mar 30, 2010 Issued
Array ( [id] => 8436828 [patent_doc_number] => 08284603 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-10-09 [patent_title] => 'Memory devices and operations thereof using program state determination based on data value distribution' [patent_app_type] => utility [patent_app_number] => 12/748113 [patent_app_country] => US [patent_app_date] => 2010-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 3361 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12748113 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/748113
Memory devices and operations thereof using program state determination based on data value distribution Mar 25, 2010 Issued
Array ( [id] => 6227622 [patent_doc_number] => 20100182822 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-07-22 [patent_title] => 'DEVICE AND METHOD FOR USING DYNAMIC CELL PLATE SENSING IN A DRAM MEMORY CELL' [patent_app_type] => utility [patent_app_number] => 12/729820 [patent_app_country] => US [patent_app_date] => 2010-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7108 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0182/20100182822.pdf [firstpage_image] =>[orig_patent_app_number] => 12729820 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/729820
Device and method for using dynamic cell plate sensing in a DRAM memory cell Mar 22, 2010 Issued
Array ( [id] => 8556707 [patent_doc_number] => 08331185 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-12-11 [patent_title] => 'Semiconductor device having electrical fuses with less power consumption and interconnection arrangement' [patent_app_type] => utility [patent_app_number] => 12/723218 [patent_app_country] => US [patent_app_date] => 2010-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 34 [patent_figures_cnt] => 46 [patent_no_of_words] => 27475 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 253 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12723218 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/723218
Semiconductor device having electrical fuses with less power consumption and interconnection arrangement Mar 11, 2010 Issued
Array ( [id] => 6013204 [patent_doc_number] => 20110222338 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-09-15 [patent_title] => 'METHOD OF HANDLING REFERENCE CELLS IN NVM ARRAYS' [patent_app_type] => utility [patent_app_number] => 12/720687 [patent_app_country] => US [patent_app_date] => 2010-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4206 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0222/20110222338.pdf [firstpage_image] =>[orig_patent_app_number] => 12720687 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/720687
Method of handling reference cells in NVM arrays Mar 9, 2010 Issued
Array ( [id] => 8714675 [patent_doc_number] => 08400819 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-03-19 [patent_title] => 'Integrated circuit having variable memory array power supply voltage' [patent_app_type] => utility [patent_app_number] => 12/714079 [patent_app_country] => US [patent_app_date] => 2010-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5029 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12714079 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/714079
Integrated circuit having variable memory array power supply voltage Feb 25, 2010 Issued
Array ( [id] => 4615340 [patent_doc_number] => 07990787 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-08-02 [patent_title] => 'Memory compiler redundancy' [patent_app_type] => utility [patent_app_number] => 12/701519 [patent_app_country] => US [patent_app_date] => 2010-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6784 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/990/07990787.pdf [firstpage_image] =>[orig_patent_app_number] => 12701519 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/701519
Memory compiler redundancy Feb 4, 2010 Issued
Array ( [id] => 6316598 [patent_doc_number] => 20100195413 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-08-05 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 12/700121 [patent_app_country] => US [patent_app_date] => 2010-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4680 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0195/20100195413.pdf [firstpage_image] =>[orig_patent_app_number] => 12700121 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/700121
Mode register output circuit Feb 3, 2010 Issued
Array ( [id] => 10053284 [patent_doc_number] => 09093163 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-07-28 [patent_title] => 'Magnetoresistive device' [patent_app_type] => utility [patent_app_number] => 12/687550 [patent_app_country] => US [patent_app_date] => 2010-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 49 [patent_no_of_words] => 17453 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12687550 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/687550
Magnetoresistive device Jan 13, 2010 Issued
Array ( [id] => 8341554 [patent_doc_number] => 08243485 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-08-14 [patent_title] => 'Semiconductor apparatus and chip selection method thereof' [patent_app_type] => utility [patent_app_number] => 12/650501 [patent_app_country] => US [patent_app_date] => 2009-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 4311 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12650501 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/650501
Semiconductor apparatus and chip selection method thereof Dec 29, 2009 Issued
Array ( [id] => 8295724 [patent_doc_number] => 08223523 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-07-17 [patent_title] => 'Semiconductor apparatus and chip selection method thereof' [patent_app_type] => utility [patent_app_number] => 12/650507 [patent_app_country] => US [patent_app_date] => 2009-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3681 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12650507 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/650507
Semiconductor apparatus and chip selection method thereof Dec 29, 2009 Issued
Array ( [id] => 5966878 [patent_doc_number] => 20110149655 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-06-23 [patent_title] => 'Non-volatile memory cell array' [patent_app_type] => utility [patent_app_number] => 12/655157 [patent_app_country] => US [patent_app_date] => 2009-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5572 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0149/20110149655.pdf [firstpage_image] =>[orig_patent_app_number] => 12655157 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/655157
Arrangement of pairs of NAND strings that share bitline contacts while utilizing distinct sources lines Dec 22, 2009 Issued
Array ( [id] => 6564332 [patent_doc_number] => 20100128507 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-05-27 [patent_title] => 'CIRCUIT PROVIDING LOAD ISOLATION AND MEMORY DOMAIN TRANSLATION FOR MEMORY MODULE' [patent_app_type] => utility [patent_app_number] => 12/629827 [patent_app_country] => US [patent_app_date] => 2009-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 20102 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0128/20100128507.pdf [firstpage_image] =>[orig_patent_app_number] => 12629827 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/629827
Circuit providing load isolation and memory domain translation for memory module Dec 1, 2009 Issued
Array ( [id] => 6361064 [patent_doc_number] => 20100073985 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-03-25 [patent_title] => 'METHOD FOR OPERATING ONE-TIME PROGRAMMABLE READ-ONLY MEMORY' [patent_app_type] => utility [patent_app_number] => 12/627244 [patent_app_country] => US [patent_app_date] => 2009-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3512 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0073/20100073985.pdf [firstpage_image] =>[orig_patent_app_number] => 12627244 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/627244
Method for operating one-time programmable read-only memory Nov 29, 2009 Issued
Array ( [id] => 7765465 [patent_doc_number] => 08116133 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-02-14 [patent_title] => 'Maintenance operations for multi-level data storage cells' [patent_app_type] => utility [patent_app_number] => 12/624020 [patent_app_country] => US [patent_app_date] => 2009-11-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 18 [patent_no_of_words] => 18560 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/116/08116133.pdf [firstpage_image] =>[orig_patent_app_number] => 12624020 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/624020
Maintenance operations for multi-level data storage cells Nov 22, 2009 Issued
Array ( [id] => 6530469 [patent_doc_number] => 20100124123 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-05-20 [patent_title] => 'Nonvolatile Memory Device with Incremental Step Pulse Programming' [patent_app_type] => utility [patent_app_number] => 12/619227 [patent_app_country] => US [patent_app_date] => 2009-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5876 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0124/20100124123.pdf [firstpage_image] =>[orig_patent_app_number] => 12619227 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/619227
Nonvolatile memory device with incremental step pulse programming Nov 15, 2009 Issued
Array ( [id] => 6053793 [patent_doc_number] => 20110110153 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-05-12 [patent_title] => 'DATA STATE-DEPENDENT CHANNEL BOOSTING TO REDUCE CHANNEL-TO-FLOATING GATE COUPLING IN MEMORY' [patent_app_type] => utility [patent_app_number] => 12/616269 [patent_app_country] => US [patent_app_date] => 2009-11-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 15357 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0110/20110110153.pdf [firstpage_image] =>[orig_patent_app_number] => 12616269 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/616269
Data state-dependent channel boosting to reduce channel-to-floating gate coupling in memory Nov 10, 2009 Issued
Array ( [id] => 6530446 [patent_doc_number] => 20100124121 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-05-20 [patent_title] => 'METHOD OF ERASING FLASH MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 12/613195 [patent_app_country] => US [patent_app_date] => 2009-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3073 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0124/20100124121.pdf [firstpage_image] =>[orig_patent_app_number] => 12613195 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/613195
METHOD OF ERASING FLASH MEMORY DEVICE Nov 4, 2009 Abandoned
Array ( [id] => 7536439 [patent_doc_number] => 08050078 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-11-01 [patent_title] => 'Nanowire-based memristor devices' [patent_app_type] => utility [patent_app_number] => 12/606871 [patent_app_country] => US [patent_app_date] => 2009-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 4913 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/050/08050078.pdf [firstpage_image] =>[orig_patent_app_number] => 12606871 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/606871
Nanowire-based memristor devices Oct 26, 2009 Issued
Menu