Search

Alexander Sofocleous

Examiner (ID: 721)

Most Active Art Unit
2824
Art Unit(s)
2825, 2824, 2895
Total Applications
473
Issued Applications
387
Pending Applications
11
Abandoned Applications
76

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4522156 [patent_doc_number] => 07911837 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-03-22 [patent_title] => 'Multi-state memory cell with asymmetric charge trapping' [patent_app_type] => utility [patent_app_number] => 12/581674 [patent_app_country] => US [patent_app_date] => 2009-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 3128 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/911/07911837.pdf [firstpage_image] =>[orig_patent_app_number] => 12581674 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/581674
Multi-state memory cell with asymmetric charge trapping Oct 18, 2009 Issued
Array ( [id] => 6589349 [patent_doc_number] => 20100097862 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-04-22 [patent_title] => 'FLASH MEMORY DEVICES WITH MEMORY CELLS STRINGS INCLUDING DUMMY TRANSISTORS WITH SELECTIVE THRESHOLD VOLTAGES' [patent_app_type] => utility [patent_app_number] => 12/580949 [patent_app_country] => US [patent_app_date] => 2009-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 6545 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0097/20100097862.pdf [firstpage_image] =>[orig_patent_app_number] => 12580949 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/580949
Flash memory devices with memory cells strings including dummy transistors with selective threshold voltages Oct 15, 2009 Issued
Array ( [id] => 4447808 [patent_doc_number] => 07864627 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-01-04 [patent_title] => 'Memory module decoder' [patent_app_type] => utility [patent_app_number] => 12/577682 [patent_app_country] => US [patent_app_date] => 2009-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 25 [patent_no_of_words] => 16070 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 244 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/864/07864627.pdf [firstpage_image] =>[orig_patent_app_number] => 12577682 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/577682
Memory module decoder Oct 11, 2009 Issued
Array ( [id] => 8204578 [patent_doc_number] => 08189379 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-05-29 [patent_title] => 'Reduction of read disturb errors in NAND FLASH memory' [patent_app_type] => utility [patent_app_number] => 12/577673 [patent_app_country] => US [patent_app_date] => 2009-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 18 [patent_no_of_words] => 13624 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 246 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/189/08189379.pdf [firstpage_image] =>[orig_patent_app_number] => 12577673 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/577673
Reduction of read disturb errors in NAND FLASH memory Oct 11, 2009 Issued
Array ( [id] => 4452858 [patent_doc_number] => 07965547 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-06-21 [patent_title] => 'Arrangement and method for controlling a micromechanical element' [patent_app_type] => utility [patent_app_number] => 12/576267 [patent_app_country] => US [patent_app_date] => 2009-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 3481 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/965/07965547.pdf [firstpage_image] =>[orig_patent_app_number] => 12576267 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/576267
Arrangement and method for controlling a micromechanical element Oct 8, 2009 Issued
Array ( [id] => 8019769 [patent_doc_number] => 08139393 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-03-20 [patent_title] => 'Method and apparatus for non-volatile multi-bit memory' [patent_app_type] => utility [patent_app_number] => 12/576212 [patent_app_country] => US [patent_app_date] => 2009-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 16 [patent_no_of_words] => 5382 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/139/08139393.pdf [firstpage_image] =>[orig_patent_app_number] => 12576212 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/576212
Method and apparatus for non-volatile multi-bit memory Oct 7, 2009 Issued
Array ( [id] => 8154805 [patent_doc_number] => 08169833 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-05-01 [patent_title] => 'Partitioning process to improve memory cell retention' [patent_app_type] => utility [patent_app_number] => 12/572182 [patent_app_country] => US [patent_app_date] => 2009-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3777 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/169/08169833.pdf [firstpage_image] =>[orig_patent_app_number] => 12572182 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/572182
Partitioning process to improve memory cell retention Sep 30, 2009 Issued
Array ( [id] => 8534700 [patent_doc_number] => 08310859 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-11-13 [patent_title] => 'Semiconductor memory device having balancing capacitors' [patent_app_type] => utility [patent_app_number] => 12/570159 [patent_app_country] => US [patent_app_date] => 2009-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 2625 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12570159 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/570159
Semiconductor memory device having balancing capacitors Sep 29, 2009 Issued
Array ( [id] => 6517801 [patent_doc_number] => 20100014359 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-01-21 [patent_title] => 'OPERATING METHOD OF NON-VOLATILE MEMORY' [patent_app_type] => utility [patent_app_number] => 12/565778 [patent_app_country] => US [patent_app_date] => 2009-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 8727 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0014/20100014359.pdf [firstpage_image] =>[orig_patent_app_number] => 12565778 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/565778
Operating method of non-volatile memory Sep 23, 2009 Issued
Array ( [id] => 6233436 [patent_doc_number] => 20100265767 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-10-21 [patent_title] => 'NONVOLATILE SEMICONDUCTOR MEMORY DEVICE, METHOD OF FABRICATING THE NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND PROCESS OF WRITING DATA ON THE NONVOLATILE SEMICONDUCTOR MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 12/562479 [patent_app_country] => US [patent_app_date] => 2009-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 10953 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0265/20100265767.pdf [firstpage_image] =>[orig_patent_app_number] => 12562479 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/562479
Nonvolatile semiconductor memory device, method of fabricating the nonvolatile semiconductor memory device and process of writing data on the nonvolatile semiconductor memory device Sep 17, 2009 Issued
Array ( [id] => 6474872 [patent_doc_number] => 20100008153 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-01-14 [patent_title] => 'METHOD FOR OPERATING NONVOLATITLE MEMORY ARRAY' [patent_app_type] => utility [patent_app_number] => 12/561849 [patent_app_country] => US [patent_app_date] => 2009-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5988 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0008/20100008153.pdf [firstpage_image] =>[orig_patent_app_number] => 12561849 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/561849
Method for operating nonvolatitle memory array Sep 16, 2009 Issued
Array ( [id] => 6201140 [patent_doc_number] => 20110063926 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-03-17 [patent_title] => 'Write Through Speed Up for Memory Circuit' [patent_app_type] => utility [patent_app_number] => 12/558615 [patent_app_country] => US [patent_app_date] => 2009-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1166 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0063/20110063926.pdf [firstpage_image] =>[orig_patent_app_number] => 12558615 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/558615
Write Through Speed Up for Memory Circuit Sep 13, 2009 Abandoned
Array ( [id] => 5463227 [patent_doc_number] => 20090323427 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-12-31 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 12/555600 [patent_app_country] => US [patent_app_date] => 2009-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 13633 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0323/20090323427.pdf [firstpage_image] =>[orig_patent_app_number] => 12555600 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/555600
SEMICONDUCTOR MEMORY DEVICE Sep 7, 2009 Abandoned
Array ( [id] => 5467394 [patent_doc_number] => 20090327594 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-12-31 [patent_title] => 'APPARATUS AND METHODS FOR PROGRAMMING MULTILEVEL-CELL NAND MEMORY DEVICES' [patent_app_type] => utility [patent_app_number] => 12/552601 [patent_app_country] => US [patent_app_date] => 2009-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4428 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0327/20090327594.pdf [firstpage_image] =>[orig_patent_app_number] => 12552601 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/552601
Apparatus and methods for programming multilevel-cell NAND memory devices Sep 1, 2009 Issued
Array ( [id] => 7524021 [patent_doc_number] => 08027185 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-09-27 [patent_title] => 'Techniques for electrically characterizing tunnel junction film stacks with little or no processing' [patent_app_type] => utility [patent_app_number] => 12/539068 [patent_app_country] => US [patent_app_date] => 2009-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 22 [patent_no_of_words] => 10045 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/027/08027185.pdf [firstpage_image] =>[orig_patent_app_number] => 12539068 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/539068
Techniques for electrically characterizing tunnel junction film stacks with little or no processing Aug 10, 2009 Issued
Array ( [id] => 8399812 [patent_doc_number] => 08270200 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-09-18 [patent_title] => 'Nanoscale three-terminal switching device' [patent_app_type] => utility [patent_app_number] => 12/512230 [patent_app_country] => US [patent_app_date] => 2009-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 4210 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12512230 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/512230
Nanoscale three-terminal switching device Jul 29, 2009 Issued
Array ( [id] => 8912352 [patent_doc_number] => 08484428 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-07-09 [patent_title] => 'Enhanced block copy' [patent_app_type] => utility [patent_app_number] => 12/512765 [patent_app_country] => US [patent_app_date] => 2009-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 9483 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12512765 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/512765
Enhanced block copy Jul 29, 2009 Issued
Array ( [id] => 5366219 [patent_doc_number] => 20090303778 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-12-10 [patent_title] => 'Methods and Apparatus for Varying a Supply Voltage or Reference Voltage Using Independent Control of Diode Voltage in Asymmetrical Double-Gate Devices' [patent_app_type] => utility [patent_app_number] => 12/511666 [patent_app_country] => US [patent_app_date] => 2009-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3027 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0303/20090303778.pdf [firstpage_image] =>[orig_patent_app_number] => 12511666 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/511666
Methods and apparatus for varying a supply voltage or reference voltage using independent control of diode voltage in asymmetrical double-gate devices Jul 28, 2009 Issued
Array ( [id] => 9029548 [patent_doc_number] => 08539145 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-09-17 [patent_title] => 'Increasing the number of ranks per channel' [patent_app_type] => utility [patent_app_number] => 12/510822 [patent_app_country] => US [patent_app_date] => 2009-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6137 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 309 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12510822 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/510822
Increasing the number of ranks per channel Jul 27, 2009 Issued
Array ( [id] => 9141869 [patent_doc_number] => 08582343 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-11-12 [patent_title] => 'Semiconductor storage device, semiconductor storage device manufacturing method and package resin forming method' [patent_app_type] => utility [patent_app_number] => 12/503357 [patent_app_country] => US [patent_app_date] => 2009-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 33 [patent_figures_cnt] => 33 [patent_no_of_words] => 8882 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12503357 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/503357
Semiconductor storage device, semiconductor storage device manufacturing method and package resin forming method Jul 14, 2009 Issued
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