
Alexander Sofocleous
Examiner (ID: 721)
| Most Active Art Unit | 2824 |
| Art Unit(s) | 2825, 2824, 2895 |
| Total Applications | 473 |
| Issued Applications | 387 |
| Pending Applications | 11 |
| Abandoned Applications | 76 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 8447697
[patent_doc_number] => 08289756
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2012-10-16
[patent_title] => 'Non volatile memory including stabilizing structures'
[patent_app_type] => utility
[patent_app_number] => 12/502213
[patent_app_country] => US
[patent_app_date] => 2009-07-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 22
[patent_no_of_words] => 6641
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 84
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12502213
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/502213 | Non volatile memory including stabilizing structures | Jul 12, 2009 | Issued |
Array
(
[id] => 6371260
[patent_doc_number] => 20100315139
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-12-16
[patent_title] => 'SEMICONDUCTOR MEMORY DEVICE'
[patent_app_type] => utility
[patent_app_number] => 12/494403
[patent_app_country] => US
[patent_app_date] => 2009-06-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 4048
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0315/20100315139.pdf
[firstpage_image] =>[orig_patent_app_number] => 12494403
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/494403 | Semiconductor memory device and method for generating output enable signal | Jun 29, 2009 | Issued |
Array
(
[id] => 5456999
[patent_doc_number] => 20090257151
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-10-15
[patent_title] => 'Thin seeded Co/Ni multilayer film with perpendicular anisotropy for spintronic device applications'
[patent_app_type] => utility
[patent_app_number] => 12/456621
[patent_app_country] => US
[patent_app_date] => 2009-06-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 8188
[patent_no_of_claims] => 29
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0257/20090257151.pdf
[firstpage_image] =>[orig_patent_app_number] => 12456621
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/456621 | Thin seeded Co/Ni multilayer film with perpendicular anisotropy for spintronic device applications | Jun 18, 2009 | Issued |
Array
(
[id] => 6602562
[patent_doc_number] => 20100309714
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-12-09
[patent_title] => 'METHODS, STRUCTURES, AND DEVICES FOR REDUCING OPERATIONAL ENERGY IN PHASE CHANGE MEMORY'
[patent_app_type] => utility
[patent_app_number] => 12/480041
[patent_app_country] => US
[patent_app_date] => 2009-06-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 7431
[patent_no_of_claims] => 28
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0309/20100309714.pdf
[firstpage_image] =>[orig_patent_app_number] => 12480041
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/480041 | Methods, structures, and devices for reducing operational energy in phase change memory | Jun 7, 2009 | Issued |
Array
(
[id] => 7546725
[patent_doc_number] => 08054702
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-11-08
[patent_title] => 'Semiconductor memory device with signal aligning circuit'
[patent_app_type] => utility
[patent_app_number] => 12/472252
[patent_app_country] => US
[patent_app_date] => 2009-05-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 11
[patent_no_of_words] => 6452
[patent_no_of_claims] => 46
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 100
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/08/054/08054702.pdf
[firstpage_image] =>[orig_patent_app_number] => 12472252
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/472252 | Semiconductor memory device with signal aligning circuit | May 25, 2009 | Issued |
Array
(
[id] => 4452841
[patent_doc_number] => 07965531
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-06-21
[patent_title] => 'Memory module and memory device'
[patent_app_type] => utility
[patent_app_number] => 12/435168
[patent_app_country] => US
[patent_app_date] => 2009-05-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 40
[patent_figures_cnt] => 40
[patent_no_of_words] => 15538
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 172
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/965/07965531.pdf
[firstpage_image] =>[orig_patent_app_number] => 12435168
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/435168 | Memory module and memory device | May 3, 2009 | Issued |
Array
(
[id] => 6421535
[patent_doc_number] => 20100142296
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-06-10
[patent_title] => 'SEMICONDUCTOR MEMORY DEVICE AND DELAY LOCKED LOOP CONTROL METHOD THEREOF'
[patent_app_type] => utility
[patent_app_number] => 12/429381
[patent_app_country] => US
[patent_app_date] => 2009-04-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 2794
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0142/20100142296.pdf
[firstpage_image] =>[orig_patent_app_number] => 12429381
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/429381 | Semiconductor memory device and delay locked loop control method thereof | Apr 23, 2009 | Issued |
Array
(
[id] => 5493358
[patent_doc_number] => 20090261386
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-10-22
[patent_title] => 'SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND METHOD OF ARRANGING WIRINGS IN THE SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE'
[patent_app_type] => utility
[patent_app_number] => 12/426444
[patent_app_country] => US
[patent_app_date] => 2009-04-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 12704
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0261/20090261386.pdf
[firstpage_image] =>[orig_patent_app_number] => 12426444
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/426444 | Semiconductor integrated circuit device and method of arranging wirings in the semiconductor integrated circuit device | Apr 19, 2009 | Issued |
Array
(
[id] => 8106499
[patent_doc_number] => 08154901
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2012-04-10
[patent_title] => 'Circuit providing load isolation and noise reduction'
[patent_app_type] => utility
[patent_app_number] => 12/422853
[patent_app_country] => US
[patent_app_date] => 2009-04-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 10
[patent_no_of_words] => 9411
[patent_no_of_claims] => 31
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 17
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/08/154/08154901.pdf
[firstpage_image] =>[orig_patent_app_number] => 12422853
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/422853 | Circuit providing load isolation and noise reduction | Apr 12, 2009 | Issued |
Array
(
[id] => 46570
[patent_doc_number] => 07778107
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-08-17
[patent_title] => 'Decoding control with address transition detection in page erase function'
[patent_app_type] => utility
[patent_app_number] => 12/416512
[patent_app_country] => US
[patent_app_date] => 2009-04-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 13
[patent_no_of_words] => 8212
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 247
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/778/07778107.pdf
[firstpage_image] =>[orig_patent_app_number] => 12416512
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/416512 | Decoding control with address transition detection in page erase function | Mar 31, 2009 | Issued |
Array
(
[id] => 5478754
[patent_doc_number] => 20090201711
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-08-13
[patent_title] => 'MEMORY MODULE WITH A CIRCUIT PROVIDING LOAD ISOLATION AND MEMORY DOMAIN TRANSLATION'
[patent_app_type] => utility
[patent_app_number] => 12/408652
[patent_app_country] => US
[patent_app_date] => 2009-03-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 24
[patent_figures_cnt] => 24
[patent_no_of_words] => 20081
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0201/20090201711.pdf
[firstpage_image] =>[orig_patent_app_number] => 12408652
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/408652 | Memory module with a circuit providing load isolation and memory domain translation | Mar 19, 2009 | Issued |
Array
(
[id] => 4435928
[patent_doc_number] => 07969793
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-06-28
[patent_title] => 'Register configuration control device, register configuration control method, and program for implementing the method'
[patent_app_type] => utility
[patent_app_number] => 12/389862
[patent_app_country] => US
[patent_app_date] => 2009-02-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 22
[patent_figures_cnt] => 24
[patent_no_of_words] => 13041
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 231
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/969/07969793.pdf
[firstpage_image] =>[orig_patent_app_number] => 12389862
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/389862 | Register configuration control device, register configuration control method, and program for implementing the method | Feb 19, 2009 | Issued |
Array
(
[id] => 8154799
[patent_doc_number] => 08169827
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2012-05-01
[patent_title] => 'NAND flash memory string apparatus and methods of operation thereof'
[patent_app_type] => utility
[patent_app_number] => 12/390339
[patent_app_country] => US
[patent_app_date] => 2009-02-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 16
[patent_no_of_words] => 7201
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 146
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/08/169/08169827.pdf
[firstpage_image] =>[orig_patent_app_number] => 12390339
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/390339 | NAND flash memory string apparatus and methods of operation thereof | Feb 19, 2009 | Issued |
Array
(
[id] => 4500877
[patent_doc_number] => 07957208
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2011-06-07
[patent_title] => 'Flexible memory architectures for programmable logic devices'
[patent_app_type] => utility
[patent_app_number] => 12/389149
[patent_app_country] => US
[patent_app_date] => 2009-02-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 10
[patent_no_of_words] => 7953
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 123
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/957/07957208.pdf
[firstpage_image] =>[orig_patent_app_number] => 12389149
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/389149 | Flexible memory architectures for programmable logic devices | Feb 18, 2009 | Issued |
Array
(
[id] => 5532133
[patent_doc_number] => 20090231921
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-09-17
[patent_title] => 'MANUFACTURING METHOD OF NONVOLATILE SEMICONDUCTOR STORAGE DEVICE AND NONVOLATILE SEMICONDUCTOR STORAGE DEVICE'
[patent_app_type] => utility
[patent_app_number] => 12/389361
[patent_app_country] => US
[patent_app_date] => 2009-02-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 31
[patent_figures_cnt] => 31
[patent_no_of_words] => 22811
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0231/20090231921.pdf
[firstpage_image] =>[orig_patent_app_number] => 12389361
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/389361 | MANUFACTURING METHOD OF NONVOLATILE SEMICONDUCTOR STORAGE DEVICE AND NONVOLATILE SEMICONDUCTOR STORAGE DEVICE | Feb 18, 2009 | Abandoned |
Array
(
[id] => 114174
[patent_doc_number] => 07719885
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-05-18
[patent_title] => 'Thin film magnetic memory device having a highly integrated memory array'
[patent_app_type] => utility
[patent_app_number] => 12/370989
[patent_app_country] => US
[patent_app_date] => 2009-02-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 81
[patent_figures_cnt] => 94
[patent_no_of_words] => 34710
[patent_no_of_claims] => 1
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 314
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/719/07719885.pdf
[firstpage_image] =>[orig_patent_app_number] => 12370989
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/370989 | Thin film magnetic memory device having a highly integrated memory array | Feb 12, 2009 | Issued |
Array
(
[id] => 5389114
[patent_doc_number] => 20090206426
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-08-20
[patent_title] => 'MAGNETORESISTIVE EFFECT ELEMENT'
[patent_app_type] => utility
[patent_app_number] => 12/369555
[patent_app_country] => US
[patent_app_date] => 2009-02-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 2702
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0206/20090206426.pdf
[firstpage_image] =>[orig_patent_app_number] => 12369555
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/369555 | Magnetoresistive effect element | Feb 10, 2009 | Issued |
Array
(
[id] => 4464960
[patent_doc_number] => 07881088
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-02-01
[patent_title] => 'Content addressable memory device'
[patent_app_type] => utility
[patent_app_number] => 12/367108
[patent_app_country] => US
[patent_app_date] => 2009-02-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 29
[patent_figures_cnt] => 30
[patent_no_of_words] => 18048
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 84
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/881/07881088.pdf
[firstpage_image] =>[orig_patent_app_number] => 12367108
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/367108 | Content addressable memory device | Feb 5, 2009 | Issued |
Array
(
[id] => 35002
[patent_doc_number] => 07791951
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-09-07
[patent_title] => 'Methods of operating non-volatile memory device'
[patent_app_type] => utility
[patent_app_number] => 12/364570
[patent_app_country] => US
[patent_app_date] => 2009-02-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 35
[patent_no_of_words] => 6424
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 242
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/791/07791951.pdf
[firstpage_image] =>[orig_patent_app_number] => 12364570
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/364570 | Methods of operating non-volatile memory device | Feb 2, 2009 | Issued |
Array
(
[id] => 6446816
[patent_doc_number] => 20100169700
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-07-01
[patent_title] => 'Adaptive clock enable for memory control'
[patent_app_type] => utility
[patent_app_number] => 12/317869
[patent_app_country] => US
[patent_app_date] => 2008-12-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 2400
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0169/20100169700.pdf
[firstpage_image] =>[orig_patent_app_number] => 12317869
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/317869 | Adaptive clock enable for memory control | Dec 28, 2008 | Abandoned |