
Alexander Sofocleous
Examiner (ID: 721)
| Most Active Art Unit | 2824 |
| Art Unit(s) | 2825, 2824, 2895 |
| Total Applications | 473 |
| Issued Applications | 387 |
| Pending Applications | 11 |
| Abandoned Applications | 76 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 5548087
[patent_doc_number] => 20090157964
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-06-18
[patent_title] => 'EFFICIENT DATA STORAGE IN MULTI-PLANE MEMORY DEVICES'
[patent_app_type] => utility
[patent_app_number] => 12/332370
[patent_app_country] => US
[patent_app_date] => 2008-12-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 8364
[patent_no_of_claims] => 37
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[patent_words_short_claim] => 0
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[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0157/20090157964.pdf
[firstpage_image] =>[orig_patent_app_number] => 12332370
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/332370 | Efficient data storage in multi-plane memory devices | Dec 10, 2008 | Issued |
Array
(
[id] => 5507063
[patent_doc_number] => 20090080270
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-03-26
[patent_title] => 'MEMORY DEVICE HAVING TERMINALS FOR TRANSFERRING MULTIPLE TYPES OF DATA'
[patent_app_type] => utility
[patent_app_number] => 12/326737
[patent_app_country] => US
[patent_app_date] => 2008-12-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 22
[patent_figures_cnt] => 22
[patent_no_of_words] => 9525
[patent_no_of_claims] => 22
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[patent_maintenance] => 1
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[pdf_file] => publications/A1/0080/20090080270.pdf
[firstpage_image] =>[orig_patent_app_number] => 12326737
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/326737 | Memory device having terminals for transferring multiple types of data | Dec 1, 2008 | Issued |
Array
(
[id] => 144239
[patent_doc_number] => 07688662
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-03-30
[patent_title] => 'Method for hiding a refresh in a pseudo-static memory'
[patent_app_type] => utility
[patent_app_number] => 12/273437
[patent_app_country] => US
[patent_app_date] => 2008-11-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
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[patent_no_of_words] => 3636
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[pdf_file] => patents/07/688/07688662.pdf
[firstpage_image] =>[orig_patent_app_number] => 12273437
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/273437 | Method for hiding a refresh in a pseudo-static memory | Nov 17, 2008 | Issued |
Array
(
[id] => 6522694
[patent_doc_number] => 20100123534
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-05-20
[patent_title] => 'MAGNETIC MECHANICAL SWITCH'
[patent_app_type] => utility
[patent_app_number] => 12/272919
[patent_app_country] => US
[patent_app_date] => 2008-11-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
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[patent_no_of_words] => 3709
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[firstpage_image] =>[orig_patent_app_number] => 12272919
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/272919 | Magnetic mechanical switch | Nov 17, 2008 | Issued |
Array
(
[id] => 8561041
[patent_doc_number] => 08335108
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2012-12-18
[patent_title] => 'Bit line gate transistor structure for a multilevel, dual-sided nonvolatile memory cell NAND flash array'
[patent_app_type] => utility
[patent_app_number] => 12/291913
[patent_app_country] => US
[patent_app_date] => 2008-11-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
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[patent_no_of_words] => 18839
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[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12291913
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/291913 | Bit line gate transistor structure for a multilevel, dual-sided nonvolatile memory cell NAND flash array | Nov 13, 2008 | Issued |
Array
(
[id] => 4435870
[patent_doc_number] => 07969773
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-06-28
[patent_title] => 'Computer system with addressable storage medium'
[patent_app_type] => utility
[patent_app_number] => 12/270411
[patent_app_country] => US
[patent_app_date] => 2008-11-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/969/07969773.pdf
[firstpage_image] =>[orig_patent_app_number] => 12270411
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/270411 | Computer system with addressable storage medium | Nov 12, 2008 | Issued |
Array
(
[id] => 161392
[patent_doc_number] => 07675809
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-03-09
[patent_title] => 'Memory compiler redundancy'
[patent_app_type] => utility
[patent_app_number] => 12/268968
[patent_app_country] => US
[patent_app_date] => 2008-11-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/675/07675809.pdf
[firstpage_image] =>[orig_patent_app_number] => 12268968
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/268968 | Memory compiler redundancy | Nov 10, 2008 | Issued |
Array
(
[id] => 4625581
[patent_doc_number] => 08004887
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-08-23
[patent_title] => 'Configurable digital and analog input/output interface in a memory device'
[patent_app_type] => utility
[patent_app_number] => 12/108105
[patent_app_country] => US
[patent_app_date] => 2008-11-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/08/004/08004887.pdf
[firstpage_image] =>[orig_patent_app_number] => 12108105
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/108105 | Configurable digital and analog input/output interface in a memory device | Nov 6, 2008 | Issued |
Array
(
[id] => 6330919
[patent_doc_number] => 20100115180
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-05-06
[patent_title] => 'MEMORY MODULE INCLUDING ENVIRONMENTAL OPTIMIZATION'
[patent_app_type] => utility
[patent_app_number] => 12/262063
[patent_app_country] => US
[patent_app_date] => 2008-10-30
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[pdf_file] => publications/A1/0115/20100115180.pdf
[firstpage_image] =>[orig_patent_app_number] => 12262063
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/262063 | Memory module including environmental optimization | Oct 29, 2008 | Issued |
Array
(
[id] => 4491736
[patent_doc_number] => 07903456
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-03-08
[patent_title] => 'Superconducting circuit for high-speed lookup table'
[patent_app_type] => utility
[patent_app_number] => 12/258682
[patent_app_country] => US
[patent_app_date] => 2008-10-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
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[patent_no_of_words] => 3774
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[pdf_file] => patents/07/903/07903456.pdf
[firstpage_image] =>[orig_patent_app_number] => 12258682
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/258682 | Superconducting circuit for high-speed lookup table | Oct 26, 2008 | Issued |
Array
(
[id] => 5463742
[patent_doc_number] => 20090323942
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-12-31
[patent_title] => 'METHOD FOR PAGE- AND BLOCK BASED SCRAMBLING IN NON-VOLATILE MEMORY'
[patent_app_type] => utility
[patent_app_number] => 12/251820
[patent_app_country] => US
[patent_app_date] => 2008-10-15
[patent_effective_date] => 0000-00-00
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[pdf_file] => publications/A1/0323/20090323942.pdf
[firstpage_image] =>[orig_patent_app_number] => 12251820
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/251820 | Method for page- and block based scrambling in non-volatile memory | Oct 14, 2008 | Issued |
Array
(
[id] => 7704038
[patent_doc_number] => 08089801
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2012-01-03
[patent_title] => 'Semiconductor memory device and method of forming the same'
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[pdf_file] => patents/08/089/08089801.pdf
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/285619 | Semiconductor memory device and method of forming the same | Oct 8, 2008 | Issued |
Array
(
[id] => 4435844
[patent_doc_number] => 07969765
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-06-28
[patent_title] => 'Sense amplifier for semiconductor memory device'
[patent_app_type] => utility
[patent_app_number] => 12/285527
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/285527 | Sense amplifier for semiconductor memory device | Oct 7, 2008 | Issued |
Array
(
[id] => 225900
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/247091 | Sense amplifier circuit | Oct 6, 2008 | Issued |
Array
(
[id] => 5442855
[patent_doc_number] => 20090094494
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[patent_title] => 'SEMICONDUCTOR INTEGRATED CIRCUIT AND METHOD OF TESTING SAME'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/245395 | SEMICONDUCTOR INTEGRATED CIRCUIT AND METHOD OF TESTING SAME | Oct 2, 2008 | Abandoned |
Array
(
[id] => 35030
[patent_doc_number] => 07791958
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/243116 | Pseudo differential output buffer, memory chip and memory system | Sep 30, 2008 | Issued |
Array
(
[id] => 4435866
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[patent_title] => 'Semiconductor device with thermally coupled phase change layers'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/242620 | Semiconductor device with thermally coupled phase change layers | Sep 29, 2008 | Issued |
Array
(
[id] => 5463240
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[patent_title] => 'Data processing device and method of reading trimming data'
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Array
(
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[patent_title] => 'MEMORY DEVICE HAVING DATA PATHS WITH MULTIPLE SPEEDS'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/201405 | Memory device having data paths with multiple speeds | Aug 28, 2008 | Issued |
Array
(
[id] => 4620433
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[patent_issue_date] => 2011-08-16
[patent_title] => 'RAM macro and timing generating circuit thereof'
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[pdf_file] => patents/08/000/08000157.pdf
[firstpage_image] =>[orig_patent_app_number] => 12198373
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/198373 | RAM macro and timing generating circuit thereof | Aug 25, 2008 | Issued |