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Alfonso Garcia

Examiner (ID: 9816)

Most Active Art Unit
2303
Art Unit(s)
2303, 2512
Total Applications
441
Issued Applications
377
Pending Applications
0
Abandoned Applications
64

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 2682828 [patent_doc_number] => 05027326 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-06-25 [patent_title] => 'Self-timed sequential access multiport memory' [patent_app_type] => 1 [patent_app_number] => 7/269907 [patent_app_country] => US [patent_app_date] => 1988-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 8457 [patent_no_of_claims] => 47 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/027/05027326.pdf [firstpage_image] =>[orig_patent_app_number] => 269907 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/269907
Self-timed sequential access multiport memory Nov 9, 1988 Issued
Array ( [id] => 2692213 [patent_doc_number] => 05046051 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-09-03 [patent_title] => 'Serial memory with address counter which can be preset using a multi-purpose input, and picture memory apparatus using same' [patent_app_type] => 1 [patent_app_number] => 7/269229 [patent_app_country] => US [patent_app_date] => 1988-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 1876 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/046/05046051.pdf [firstpage_image] =>[orig_patent_app_number] => 269229 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/269229
Serial memory with address counter which can be preset using a multi-purpose input, and picture memory apparatus using same Nov 8, 1988 Issued
Array ( [id] => 2640567 [patent_doc_number] => 04958324 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-09-18 [patent_title] => 'Method for the testing of electrically programmable memory cells, and corresponding integrated circuit' [patent_app_type] => 1 [patent_app_number] => 7/269169 [patent_app_country] => US [patent_app_date] => 1988-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3739 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/958/04958324.pdf [firstpage_image] =>[orig_patent_app_number] => 269169 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/269169
Method for the testing of electrically programmable memory cells, and corresponding integrated circuit Nov 8, 1988 Issued
Array ( [id] => 2608359 [patent_doc_number] => 04922462 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-05-01 [patent_title] => 'Reversible memory structure for optical reading and writing and which is capable of erasure' [patent_app_type] => 1 [patent_app_number] => 7/270445 [patent_app_country] => US [patent_app_date] => 1988-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 24 [patent_no_of_words] => 9966 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 206 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/922/04922462.pdf [firstpage_image] =>[orig_patent_app_number] => 270445 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/270445
Reversible memory structure for optical reading and writing and which is capable of erasure Nov 8, 1988 Issued
Array ( [id] => 2664853 [patent_doc_number] => 04972376 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-11-20 [patent_title] => 'Self-refresh system for use in a field memory device operating without reliance upon external control' [patent_app_type] => 1 [patent_app_number] => 7/268499 [patent_app_country] => US [patent_app_date] => 1988-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2017 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 206 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/972/04972376.pdf [firstpage_image] =>[orig_patent_app_number] => 268499 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/268499
Self-refresh system for use in a field memory device operating without reliance upon external control Nov 7, 1988 Issued
Array ( [id] => 2678413 [patent_doc_number] => 04954992 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-09-04 [patent_title] => 'Random access memory having separate read out and write in bus lines for reduced access time and operating method therefor' [patent_app_type] => 1 [patent_app_number] => 7/269757 [patent_app_country] => US [patent_app_date] => 1988-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 46 [patent_no_of_words] => 12694 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 326 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/954/04954992.pdf [firstpage_image] =>[orig_patent_app_number] => 269757 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/269757
Random access memory having separate read out and write in bus lines for reduced access time and operating method therefor Nov 7, 1988 Issued
Array ( [id] => 2676802 [patent_doc_number] => 04935896 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-06-19 [patent_title] => 'Semiconductor memory device having three-transistor type memory cells structure without additional gates' [patent_app_type] => 1 [patent_app_number] => 7/266057 [patent_app_country] => US [patent_app_date] => 1988-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 5260 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 260 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/935/04935896.pdf [firstpage_image] =>[orig_patent_app_number] => 266057 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/266057
Semiconductor memory device having three-transistor type memory cells structure without additional gates Nov 1, 1988 Issued
Array ( [id] => 2703287 [patent_doc_number] => 05020030 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-05-28 [patent_title] => 'Nonvolatile SNOS memory cell with induced capacitor' [patent_app_type] => 1 [patent_app_number] => 7/265409 [patent_app_country] => US [patent_app_date] => 1988-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 24 [patent_no_of_words] => 4436 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 26 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/020/05020030.pdf [firstpage_image] =>[orig_patent_app_number] => 265409 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/265409
Nonvolatile SNOS memory cell with induced capacitor Oct 30, 1988 Issued
Array ( [id] => 2637955 [patent_doc_number] => 04907203 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-03-06 [patent_title] => 'Semiconductor memory device with changeable word organization modes including a test mode' [patent_app_type] => 1 [patent_app_number] => 7/264189 [patent_app_country] => US [patent_app_date] => 1988-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 23 [patent_no_of_words] => 8175 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/907/04907203.pdf [firstpage_image] =>[orig_patent_app_number] => 264189 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/264189
Semiconductor memory device with changeable word organization modes including a test mode Oct 30, 1988 Issued
Array ( [id] => 2566382 [patent_doc_number] => 04942554 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-07-17 [patent_title] => 'Three-dimensional, one-transistor cell arrangement for dynamic semiconductor memories comprising trench capacitor and method for manufacturing same' [patent_app_type] => 1 [patent_app_number] => 7/259699 [patent_app_country] => US [patent_app_date] => 1988-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 10 [patent_no_of_words] => 2562 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 285 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/942/04942554.pdf [firstpage_image] =>[orig_patent_app_number] => 259699 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/259699
Three-dimensional, one-transistor cell arrangement for dynamic semiconductor memories comprising trench capacitor and method for manufacturing same Oct 17, 1988 Issued
Array ( [id] => 2618746 [patent_doc_number] => 04903241 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-02-20 [patent_title] => 'Read circuit having a limited-bandwidth amplifier for holding the output of a delay circuit' [patent_app_type] => 1 [patent_app_number] => 7/253539 [patent_app_country] => US [patent_app_date] => 1988-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 4 [patent_no_of_words] => 1900 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 259 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/903/04903241.pdf [firstpage_image] =>[orig_patent_app_number] => 253539 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/253539
Read circuit having a limited-bandwidth amplifier for holding the output of a delay circuit Oct 4, 1988 Issued
Array ( [id] => 2596904 [patent_doc_number] => 04928261 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-05-22 [patent_title] => 'CMOS read-only memory with static operation' [patent_app_type] => 1 [patent_app_number] => 7/245655 [patent_app_country] => US [patent_app_date] => 1988-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 3 [patent_no_of_words] => 1891 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/928/04928261.pdf [firstpage_image] =>[orig_patent_app_number] => 245655 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/245655
CMOS read-only memory with static operation Sep 15, 1988 Issued
Array ( [id] => 2612858 [patent_doc_number] => 04912680 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-03-27 [patent_title] => 'Image memory having plural input registers and output registers to provide random and serial accesses' [patent_app_type] => 1 [patent_app_number] => 7/239749 [patent_app_country] => US [patent_app_date] => 1988-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 6670 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 221 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/912/04912680.pdf [firstpage_image] =>[orig_patent_app_number] => 239749 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/239749
Image memory having plural input registers and output registers to provide random and serial accesses Sep 1, 1988 Issued
Array ( [id] => 2604129 [patent_doc_number] => 04933905 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-06-12 [patent_title] => 'Semiconductor memory device for reducing power dissipation during a write operation' [patent_app_type] => 1 [patent_app_number] => 7/229879 [patent_app_country] => US [patent_app_date] => 1988-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2225 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 249 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/933/04933905.pdf [firstpage_image] =>[orig_patent_app_number] => 229879 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/229879
Semiconductor memory device for reducing power dissipation during a write operation Aug 7, 1988 Issued
Array ( [id] => 2595610 [patent_doc_number] => 04926385 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-05-15 [patent_title] => 'Semiconductor memory device with cache memory addressable by block within each column' [patent_app_type] => 1 [patent_app_number] => 7/228589 [patent_app_country] => US [patent_app_date] => 1988-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 4010 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 277 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/926/04926385.pdf [firstpage_image] =>[orig_patent_app_number] => 228589 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/228589
Semiconductor memory device with cache memory addressable by block within each column Aug 4, 1988 Issued
Array ( [id] => 2595591 [patent_doc_number] => 04926384 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-05-15 [patent_title] => 'Static ram with write recovery in selected portion of memory array' [patent_app_type] => 1 [patent_app_number] => 7/224929 [patent_app_country] => US [patent_app_date] => 1988-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 14 [patent_no_of_words] => 7966 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/926/04926384.pdf [firstpage_image] =>[orig_patent_app_number] => 224929 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/224929
Static ram with write recovery in selected portion of memory array Jul 26, 1988 Issued
Array ( [id] => 2595464 [patent_doc_number] => 04908798 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-03-13 [patent_title] => 'Semiconductor memory device with memory cell arrays and a redundant memory cell array associated with a small number of write-in and sense amplifying circuits' [patent_app_type] => 1 [patent_app_number] => 7/221969 [patent_app_country] => US [patent_app_date] => 1988-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 3836 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 530 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/908/04908798.pdf [firstpage_image] =>[orig_patent_app_number] => 221969 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/221969
Semiconductor memory device with memory cell arrays and a redundant memory cell array associated with a small number of write-in and sense amplifying circuits Jul 19, 1988 Issued
07/220328 N/A Jul 17, 1988 Abandoned
Array ( [id] => 2693821 [patent_doc_number] => 04990489 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-02-05 [patent_title] => 'Read only memory device including a superconductive electrode' [patent_app_type] => 1 [patent_app_number] => 7/215802 [patent_app_country] => US [patent_app_date] => 1988-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 15 [patent_no_of_words] => 3198 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/990/04990489.pdf [firstpage_image] =>[orig_patent_app_number] => 215802 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/215802
Read only memory device including a superconductive electrode Jul 5, 1988 Issued
Array ( [id] => 2678433 [patent_doc_number] => 04954993 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-09-04 [patent_title] => 'Semiconductor integrated circuit having a plurality of circuit blocks respectively supplied with power from different power sources' [patent_app_type] => 1 [patent_app_number] => 7/214189 [patent_app_country] => US [patent_app_date] => 1988-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 2774 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/954/04954993.pdf [firstpage_image] =>[orig_patent_app_number] => 214189 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/214189
Semiconductor integrated circuit having a plurality of circuit blocks respectively supplied with power from different power sources Jun 30, 1988 Issued
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