Search

Alfredo Bermudez Lozada

Examiner (ID: 7463, Phone: (571)272-0877 , Office: P/2825 )

Most Active Art Unit
2825
Art Unit(s)
2825
Total Applications
617
Issued Applications
490
Pending Applications
86
Abandoned Applications
57

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17878776 [patent_doc_number] => 11450802 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-09-20 [patent_title] => Thermally sensitive ionic redox transistor [patent_app_type] => utility [patent_app_number] => 16/854151 [patent_app_country] => US [patent_app_date] => 2020-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 6298 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16854151 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/854151
Thermally sensitive ionic redox transistor Apr 20, 2020 Issued
Array ( [id] => 17825850 [patent_doc_number] => 11430805 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-08-30 [patent_title] => Semiconductor memory device including three-dimensional memory cell arrays [patent_app_type] => utility [patent_app_number] => 16/852990 [patent_app_country] => US [patent_app_date] => 2020-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 15 [patent_no_of_words] => 4658 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 510 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16852990 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/852990
Semiconductor memory device including three-dimensional memory cell arrays Apr 19, 2020 Issued
Array ( [id] => 16210510 [patent_doc_number] => 20200243500 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-30 [patent_title] => THREE-DIMENSIONAL SEMICONDUCTOR CHIP CONTAINING MEMORY DIE BONDED TO BOTH SIDES OF A SUPPORT DIE AND METHODS OF MAKING THE SAME [patent_app_type] => utility [patent_app_number] => 16/848137 [patent_app_country] => US [patent_app_date] => 2020-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19649 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16848137 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/848137
Three-dimensional semiconductor chip containing memory die bonded to both sides of a support die and methods of making the same Apr 13, 2020 Issued
Array ( [id] => 17158782 [patent_doc_number] => 20210319833 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-10-14 [patent_title] => APPARATUS AND METHODS FOR QUARTER BIT LINE SENSING [patent_app_type] => utility [patent_app_number] => 16/845249 [patent_app_country] => US [patent_app_date] => 2020-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14851 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16845249 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/845249
APPARATUS AND METHODS FOR QUARTER BIT LINE SENSING Apr 9, 2020 Abandoned
Array ( [id] => 16193902 [patent_doc_number] => 20200234751 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-23 [patent_title] => Memory Arrays, Ferroelectric Transistors, and Methods of Reading and Writing Relative to Memory Cells of Memory Arrays [patent_app_type] => utility [patent_app_number] => 16/838585 [patent_app_country] => US [patent_app_date] => 2020-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5835 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 224 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16838585 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/838585
Memory arrays, ferroelectric transistors, and methods of reading and writing relative to memory cells of memory arrays Apr 1, 2020 Issued
Array ( [id] => 17130069 [patent_doc_number] => 20210304838 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-30 [patent_title] => INTERCONNECTED COMMAND/ADDRESS RESOURCES [patent_app_type] => utility [patent_app_number] => 16/836646 [patent_app_country] => US [patent_app_date] => 2020-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15147 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16836646 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/836646
Interconnected command/address resources Mar 30, 2020 Issued
Array ( [id] => 16180159 [patent_doc_number] => 20200227128 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-16 [patent_title] => MEMORY DEVICES CONFIGURED TO TEST DATA PATH INTEGRITY [patent_app_type] => utility [patent_app_number] => 16/827751 [patent_app_country] => US [patent_app_date] => 2020-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3858 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 211 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16827751 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/827751
Memory devices configured to test data path integrity Mar 23, 2020 Issued
Array ( [id] => 16347747 [patent_doc_number] => 20200312398 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-10-01 [patent_title] => Ferroelectric Domain Regulated Optical Readout Mode Memory And Preparing Method Thereof [patent_app_type] => utility [patent_app_number] => 16/823410 [patent_app_country] => US [patent_app_date] => 2020-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1802 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -1 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16823410 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/823410
Ferroelectric domain regulated optical readout mode memory and preparing method thereof Mar 18, 2020 Issued
Array ( [id] => 16162677 [patent_doc_number] => 20200219571 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-09 [patent_title] => Adjustable Read Retry Order Based on Decoding Success Trend [patent_app_type] => utility [patent_app_number] => 16/824584 [patent_app_country] => US [patent_app_date] => 2020-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12757 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16824584 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/824584
Adjustable read retry order based on decoding success trend Mar 18, 2020 Issued
Array ( [id] => 16347732 [patent_doc_number] => 20200312383 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-10-01 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 16/823314 [patent_app_country] => US [patent_app_date] => 2020-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3124 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -3 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16823314 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/823314
Semiconductor device including first-in first-out circuit Mar 17, 2020 Issued
Array ( [id] => 17395700 [patent_doc_number] => 11244721 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-02-08 [patent_title] => Memory device for controlling unselected memory cells in accordance with adjacency to selected memory cell, and method for operating the same [patent_app_type] => utility [patent_app_number] => 16/821265 [patent_app_country] => US [patent_app_date] => 2020-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 18 [patent_no_of_words] => 15257 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16821265 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/821265
Memory device for controlling unselected memory cells in accordance with adjacency to selected memory cell, and method for operating the same Mar 16, 2020 Issued
Array ( [id] => 17730547 [patent_doc_number] => 11386944 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-07-12 [patent_title] => Memory device with switching element connected in series to resistance change memory element [patent_app_type] => utility [patent_app_number] => 16/821510 [patent_app_country] => US [patent_app_date] => 2020-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 20 [patent_no_of_words] => 6703 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 225 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16821510 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/821510
Memory device with switching element connected in series to resistance change memory element Mar 16, 2020 Issued
Array ( [id] => 17099959 [patent_doc_number] => 20210287750 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-16 [patent_title] => RESOURCE MANAGEMENT FOR MEMORY DIE-SPECIFIC OPERATIONS [patent_app_type] => utility [patent_app_number] => 16/818115 [patent_app_country] => US [patent_app_date] => 2020-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8631 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 43 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16818115 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/818115
Resource management for memory die-specific operations Mar 12, 2020 Issued
Array ( [id] => 16097839 [patent_doc_number] => 20200202906 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-06-25 [patent_title] => Assemblies Comprising Memory Cells and Select Gates; and Methods of Forming Assemblies [patent_app_type] => utility [patent_app_number] => 16/810058 [patent_app_country] => US [patent_app_date] => 2020-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6803 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16810058 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/810058
Assemblies comprising memory cells and select gates; and methods of forming assemblies Mar 4, 2020 Issued
Array ( [id] => 16097917 [patent_doc_number] => 20200202945 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-06-25 [patent_title] => PROGRAMMING NONVOLATILE MEMORY CELLS THROUGH A SERIES OF PREDETERMINED THRESHOLD VOLTAGES [patent_app_type] => utility [patent_app_number] => 16/804237 [patent_app_country] => US [patent_app_date] => 2020-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 20412 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16804237 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/804237
Programming nonvolatile memory cells through a series of predetermined threshold voltages Feb 27, 2020 Issued
Array ( [id] => 16315855 [patent_doc_number] => 20200294593 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-09-17 [patent_title] => ERASABLE PROGRAMMABLE NON-VOLATILE MEMORY [patent_app_type] => utility [patent_app_number] => 16/803585 [patent_app_country] => US [patent_app_date] => 2020-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6832 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 358 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16803585 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/803585
Erasable programmable non-volatile memory Feb 26, 2020 Issued
Array ( [id] => 16020371 [patent_doc_number] => 20200185029 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-06-11 [patent_title] => SEMICONDUCTOR SYSTEM INCLUDING A PHASE CHANGEABLE MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 16/790415 [patent_app_country] => US [patent_app_date] => 2020-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4826 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16790415 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/790415
Semiconductor system including a phase changeable memory device Feb 12, 2020 Issued
Array ( [id] => 18415841 [patent_doc_number] => 11670386 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-06-06 [patent_title] => Method for suppressing gate oxide tunnel current in non-volatile memory to reduce disturbs [patent_app_type] => utility [patent_app_number] => 16/734517 [patent_app_country] => US [patent_app_date] => 2020-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 7864 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16734517 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/734517
Method for suppressing gate oxide tunnel current in non-volatile memory to reduce disturbs Jan 5, 2020 Issued
Array ( [id] => 17032557 [patent_doc_number] => 11094374 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-08-17 [patent_title] => Write data processing circuits and methods associated with computational memory cells [patent_app_type] => utility [patent_app_number] => 16/727805 [patent_app_country] => US [patent_app_date] => 2019-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 8163 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 245 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16727805 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/727805
Write data processing circuits and methods associated with computational memory cells Dec 25, 2019 Issued
Array ( [id] => 16208850 [patent_doc_number] => 20200241840 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-30 [patent_title] => ARITHMETIC DEVICE [patent_app_type] => utility [patent_app_number] => 16/724800 [patent_app_country] => US [patent_app_date] => 2019-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19457 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16724800 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/724800
Arithmetic device having magnetoresistive effect elements Dec 22, 2019 Issued
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