Search

Alfredo Bermudez Lozada

Examiner (ID: 7463, Phone: (571)272-0877 , Office: P/2825 )

Most Active Art Unit
2825
Art Unit(s)
2825
Total Applications
617
Issued Applications
490
Pending Applications
86
Abandoned Applications
57

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19696107 [patent_doc_number] => 20250014652 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-09 [patent_title] => SEMICONDUCTOR MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/888253 [patent_app_country] => US [patent_app_date] => 2024-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 22307 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 535 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18888253 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/888253
SEMICONDUCTOR MEMORY DEVICE Sep 17, 2024 Pending
Array ( [id] => 19687727 [patent_doc_number] => 20250006272 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-02 [patent_title] => NONVOLATILE MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/886210 [patent_app_country] => US [patent_app_date] => 2024-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8276 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 45 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18886210 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/886210
NONVOLATILE MEMORY DEVICE Sep 15, 2024 Pending
Array ( [id] => 19687708 [patent_doc_number] => 20250006253 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-02 [patent_title] => SYSTEMS, METHODS AND MEDIA OF OPTIMIZATION OF TEMPORARY READ ERRORS IN 3D NAND MEMORY DEVICES [patent_app_type] => utility [patent_app_number] => 18/830329 [patent_app_country] => US [patent_app_date] => 2024-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9774 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18830329 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/830329
SYSTEMS, METHODS AND MEDIA OF OPTIMIZATION OF TEMPORARY READ ERRORS IN 3D NAND MEMORY DEVICES Sep 9, 2024 Pending
Array ( [id] => 20558125 [patent_doc_number] => 20260057911 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-02-26 [patent_title] => MEMORY DEVICE AND METHOD FOR ADJUSTING SIGNAL TRANSMISSION [patent_app_type] => utility [patent_app_number] => 18/811749 [patent_app_country] => US [patent_app_date] => 2024-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18811749 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/811749
MEMORY DEVICE AND METHOD FOR ADJUSTING SIGNAL TRANSMISSION Aug 20, 2024 Pending
Array ( [id] => 19574863 [patent_doc_number] => 20240379155 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-14 [patent_title] => NON-VOLATILE MEMORY BASED COMPUTE-IN-MEMORY CELL [patent_app_type] => utility [patent_app_number] => 18/783018 [patent_app_country] => US [patent_app_date] => 2024-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12201 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18783018 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/783018
NON-VOLATILE MEMORY BASED COMPUTE-IN-MEMORY CELL Jul 23, 2024 Pending
Array ( [id] => 20002101 [patent_doc_number] => 20250140323 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-01 [patent_title] => LOGICAL BLOCK CONSTRUCTION FOR PHYSICAL BLOCKS COMPRISING MULTIPLE ERASE BLOCKS COUPLED TO A SAME STRING [patent_app_type] => utility [patent_app_number] => 18/781524 [patent_app_country] => US [patent_app_date] => 2024-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3189 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18781524 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/781524
LOGICAL BLOCK CONSTRUCTION FOR PHYSICAL BLOCKS COMPRISING MULTIPLE ERASE BLOCKS COUPLED TO A SAME STRING Jul 22, 2024 Pending
Array ( [id] => 19574886 [patent_doc_number] => 20240379178 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-14 [patent_title] => GANGED SINGLE LEVEL CELL VERIFY IN A MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/780167 [patent_app_country] => US [patent_app_date] => 2024-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10065 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18780167 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/780167
GANGED SINGLE LEVEL CELL VERIFY IN A MEMORY DEVICE Jul 21, 2024 Pending
Array ( [id] => 20488383 [patent_doc_number] => 20260024584 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-01-22 [patent_title] => HOLE PRE-CHARGE FROM BITLINE SIDE TO ENABLE FULL REVERSE ORDER PROGRAM SUB-BLOCK MODE [patent_app_type] => utility [patent_app_number] => 18/776359 [patent_app_country] => US [patent_app_date] => 2024-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10811 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18776359 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/776359
HOLE PRE-CHARGE FROM BITLINE SIDE TO ENABLE FULL REVERSE ORDER PROGRAM SUB-BLOCK MODE Jul 17, 2024 Pending
Array ( [id] => 20000782 [patent_doc_number] => 20250139004 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-01 [patent_title] => DDR BUFFER DEVICE EQUALIZATION FOR SELF-TRAINING MODE [patent_app_type] => utility [patent_app_number] => 18/768716 [patent_app_country] => US [patent_app_date] => 2024-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2442 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18768716 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/768716
DDR BUFFER DEVICE EQUALIZATION FOR SELF-TRAINING MODE Jul 9, 2024 Pending
Array ( [id] => 20461948 [patent_doc_number] => 20260011377 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-01-08 [patent_title] => ERASE METHOD FOR MEMORY DEVICE AND MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/762246 [patent_app_country] => US [patent_app_date] => 2024-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1140 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 325 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18762246 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/762246
ERASE METHOD FOR MEMORY DEVICE AND MEMORY DEVICE Jul 1, 2024 Pending
Array ( [id] => 20102874 [patent_doc_number] => 20250232810 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-17 [patent_title] => MEMORY DEVICES WITH DUAL-SIDE DISCHARGE AND METHODS FOR OPERATING THE SAME [patent_app_type] => utility [patent_app_number] => 18/760660 [patent_app_country] => US [patent_app_date] => 2024-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2323 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18760660 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/760660
MEMORY DEVICES WITH DUAL-SIDE DISCHARGE AND METHODS FOR OPERATING THE SAME Jun 30, 2024 Pending
Array ( [id] => 20124259 [patent_doc_number] => 20250239290 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-24 [patent_title] => SEMICONDUCTOR MEMORY DEVICE AND SELF-REFRESH METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/758646 [patent_app_country] => US [patent_app_date] => 2024-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4494 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18758646 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/758646
SEMICONDUCTOR MEMORY DEVICE AND SELF-REFRESH METHOD THEREOF Jun 27, 2024 Pending
Array ( [id] => 19661773 [patent_doc_number] => 20240428838 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-26 [patent_title] => SYNAPSE DEVICE INCLUDING FERROELECTRIC FIELD EFFECT TRANSISTOR AND NEURAL NETWORK APPARATUS INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 18/748706 [patent_app_country] => US [patent_app_date] => 2024-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10653 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18748706 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/748706
SYNAPSE DEVICE INCLUDING FERROELECTRIC FIELD EFFECT TRANSISTOR AND NEURAL NETWORK APPARATUS INCLUDING THE SAME Jun 19, 2024 Pending
Array ( [id] => 19500139 [patent_doc_number] => 20240339157 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-10 [patent_title] => CROSSBAR CIRCUITS FOR PERFORMING CONVOLUTION OPERATIONS [patent_app_type] => utility [patent_app_number] => 18/749166 [patent_app_country] => US [patent_app_date] => 2024-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13183 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 246 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18749166 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/749166
CROSSBAR CIRCUITS FOR PERFORMING CONVOLUTION OPERATIONS Jun 19, 2024 Pending
Array ( [id] => 19483738 [patent_doc_number] => 20240331780 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-03 [patent_title] => ADJUSTMENT OF PROGRAM VERIFY TARGETS CORRESPONDING TO A LAST PROGRAMMING DISTRIBUTION AND A PROGRAMMING DISTRIBUTION ADJACENT TO AN INITIAL PROGRAMMING DISTRIBUTION [patent_app_type] => utility [patent_app_number] => 18/738908 [patent_app_country] => US [patent_app_date] => 2024-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 20336 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18738908 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/738908
Adjustment of program verify targets corresponding to a last programming distribution and a programming distribution adjacent to an initial programming distribution Jun 9, 2024 Issued
Array ( [id] => 20806043 [patent_doc_number] => 12670955 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-06-30 [patent_title] => Analog content addressable memory cell and array for soft decision boundaries and soft decision tree computation system using the same [patent_app_type] => utility [patent_app_number] => 18/733849 [patent_app_country] => US [patent_app_date] => 2024-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 18 [patent_no_of_words] => 3036 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 200 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18733849 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/733849
Analog content addressable memory cell and array for soft decision boundaries and soft decision tree computation system using the same Jun 4, 2024 Issued
Array ( [id] => 20791096 [patent_doc_number] => 12665012 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-06-23 [patent_title] => Operation method of ferroelectric memory [patent_app_type] => utility [patent_app_number] => 18/674402 [patent_app_country] => US [patent_app_date] => 2024-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 2481 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18674402 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/674402
Operation method of ferroelectric memory May 23, 2024 Issued
Array ( [id] => 20196570 [patent_doc_number] => 20250273280 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-08-28 [patent_title] => MEMORY DEVICES, MEMORY SYSTEMS AND CONTROL METHODS THEREOF [patent_app_type] => utility [patent_app_number] => 18/672925 [patent_app_country] => US [patent_app_date] => 2024-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11556 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18672925 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/672925
MEMORY DEVICES, MEMORY SYSTEMS AND CONTROL METHODS THEREOF May 22, 2024 Pending
Array ( [id] => 19436779 [patent_doc_number] => 20240305277 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-12 [patent_title] => SEMICONDUCTOR INTEGRATED CIRCUIT [patent_app_type] => utility [patent_app_number] => 18/664387 [patent_app_country] => US [patent_app_date] => 2024-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 27852 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18664387 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/664387
Semiconductor integrated circuit May 14, 2024 Issued
Array ( [id] => 20367113 [patent_doc_number] => 20250356925 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-11-20 [patent_title] => NON-VOLATILE MEMORY WITH GROUPED BIT LINES FOR SENSING [patent_app_type] => utility [patent_app_number] => 18/663366 [patent_app_country] => US [patent_app_date] => 2024-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13092 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18663366 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/663366
NON-VOLATILE MEMORY WITH GROUPED BIT LINES FOR SENSING May 13, 2024 Pending
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