
Alfredo Bermudez Lozada
Examiner (ID: 7463, Phone: (571)272-0877 , Office: P/2825 )
| Most Active Art Unit | 2825 |
| Art Unit(s) | 2825 |
| Total Applications | 617 |
| Issued Applications | 490 |
| Pending Applications | 86 |
| Abandoned Applications | 57 |
Applications
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|---|---|---|---|
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