Search

Alfredo Bermudez Lozada

Examiner (ID: 7463, Phone: (571)272-0877 , Office: P/2825 )

Most Active Art Unit
2825
Art Unit(s)
2825
Total Applications
617
Issued Applications
490
Pending Applications
86
Abandoned Applications
57

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16372199 [patent_doc_number] => 10803965 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-10-13 [patent_title] => Semiconductor memory device and erase verify operation [patent_app_type] => utility [patent_app_number] => 16/281293 [patent_app_country] => US [patent_app_date] => 2019-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 30 [patent_no_of_words] => 18255 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 227 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16281293 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/281293
Semiconductor memory device and erase verify operation Feb 20, 2019 Issued
Array ( [id] => 14382143 [patent_doc_number] => 20190164984 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-30 [patent_title] => Virtual Ground Non-volatile Memory Array [patent_app_type] => utility [patent_app_number] => 16/264349 [patent_app_country] => US [patent_app_date] => 2019-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6577 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -35 [patent_words_short_claim] => 309 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16264349 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/264349
Virtual Ground Non-volatile Memory Array Jan 30, 2019 Abandoned
Array ( [id] => 16552838 [patent_doc_number] => 10886003 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-01-05 [patent_title] => Semiconductor memory device, operating method thereof, and memory system [patent_app_type] => utility [patent_app_number] => 16/262347 [patent_app_country] => US [patent_app_date] => 2019-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 27 [patent_no_of_words] => 15458 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 251 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16262347 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/262347
Semiconductor memory device, operating method thereof, and memory system Jan 29, 2019 Issued
Array ( [id] => 17195862 [patent_doc_number] => 11164627 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-11-02 [patent_title] => Polarity-written cell architectures for a memory device [patent_app_type] => utility [patent_app_number] => 16/257521 [patent_app_country] => US [patent_app_date] => 2019-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 26340 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 340 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16257521 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/257521
Polarity-written cell architectures for a memory device Jan 24, 2019 Issued
Array ( [id] => 15955331 [patent_doc_number] => 10665581 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-05-26 [patent_title] => Three-dimensional semiconductor chip containing memory die bonded to both sides of a support die and methods of making the same [patent_app_type] => utility [patent_app_number] => 16/255413 [patent_app_country] => US [patent_app_date] => 2019-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 41 [patent_figures_cnt] => 47 [patent_no_of_words] => 19649 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16255413 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/255413
Three-dimensional semiconductor chip containing memory die bonded to both sides of a support die and methods of making the same Jan 22, 2019 Issued
Array ( [id] => 16193916 [patent_doc_number] => 20200234765 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-23 [patent_title] => Content-Addressable Memory having Six-Transistor Content-Addressable Memory Cells [patent_app_type] => utility [patent_app_number] => 16/254611 [patent_app_country] => US [patent_app_date] => 2019-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2922 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16254611 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/254611
Content-addressable memory having six-transistor content-addressable memory cells Jan 22, 2019 Issued
Array ( [id] => 16186879 [patent_doc_number] => 10720215 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-07-21 [patent_title] => Methods and apparatus for writing nonvolatile 3D NAND flash memory using multiple-page programming [patent_app_type] => utility [patent_app_number] => 16/246378 [patent_app_country] => US [patent_app_date] => 2019-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 24 [patent_no_of_words] => 13542 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 202 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16246378 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/246378
Methods and apparatus for writing nonvolatile 3D NAND flash memory using multiple-page programming Jan 10, 2019 Issued
Array ( [id] => 14316485 [patent_doc_number] => 20190147946 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-16 [patent_title] => TUNABLE NEGATIVE BITLINE WRITE ASSIST AND BOOST ATTENUATION CIRCUIT [patent_app_type] => utility [patent_app_number] => 16/243623 [patent_app_country] => US [patent_app_date] => 2019-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5357 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16243623 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/243623
Tunable negative bitline write assist and boost attenuation circuit Jan 8, 2019 Issued
Array ( [id] => 16034535 [patent_doc_number] => 10679694 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-06-09 [patent_title] => Performance aware word line under-drive read assist scheme for high density SRAM to enable low voltage functionality [patent_app_type] => utility [patent_app_number] => 16/241349 [patent_app_country] => US [patent_app_date] => 2019-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 16 [patent_no_of_words] => 6860 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16241349 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/241349
Performance aware word line under-drive read assist scheme for high density SRAM to enable low voltage functionality Jan 6, 2019 Issued
Array ( [id] => 16566650 [patent_doc_number] => 10892024 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-01-12 [patent_title] => Scan optimization from stacking multiple reliability specifications [patent_app_type] => utility [patent_app_number] => 16/232185 [patent_app_country] => US [patent_app_date] => 2018-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 16387 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16232185 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/232185
Scan optimization from stacking multiple reliability specifications Dec 25, 2018 Issued
Array ( [id] => 15954755 [patent_doc_number] => 10665290 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-05-26 [patent_title] => Memory security techniques using auto refresh validation [patent_app_type] => utility [patent_app_number] => 16/230573 [patent_app_country] => US [patent_app_date] => 2018-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8910 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16230573 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/230573
Memory security techniques using auto refresh validation Dec 20, 2018 Issued
Array ( [id] => 14237607 [patent_doc_number] => 20190130976 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-02 [patent_title] => APPARATUSES AND METHODS USING NEGATIVE VOLTAGES IN PART OF MEMORY WRITE, READ, AND ERASE OPERATIONS [patent_app_type] => utility [patent_app_number] => 16/228428 [patent_app_country] => US [patent_app_date] => 2018-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8138 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16228428 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/228428
Apparatuses and methods using negative voltages in part of memory write, read, and erase operations Dec 19, 2018 Issued
Array ( [id] => 15856833 [patent_doc_number] => 10643711 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-05-05 [patent_title] => Workload based dynamic erase suspend adaptation [patent_app_type] => utility [patent_app_number] => 16/228599 [patent_app_country] => US [patent_app_date] => 2018-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 11876 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16228599 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/228599
Workload based dynamic erase suspend adaptation Dec 19, 2018 Issued
Array ( [id] => 16432663 [patent_doc_number] => 10832755 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-11-10 [patent_title] => Memory devices and methods of controlling an auto-refresh operation of the memory devices [patent_app_type] => utility [patent_app_number] => 16/218225 [patent_app_country] => US [patent_app_date] => 2018-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3767 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16218225 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/218225
Memory devices and methods of controlling an auto-refresh operation of the memory devices Dec 11, 2018 Issued
Array ( [id] => 16578452 [patent_doc_number] => 20210012853 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-01-14 [patent_title] => STORAGE CONTROL CIRCUIT, STORAGE APPARATUS, IMAGING APPARATUS, AND STORAGE CONTROL METHOD [patent_app_type] => utility [patent_app_number] => 16/980688 [patent_app_country] => US [patent_app_date] => 2018-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9508 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16980688 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/980688
Storage control circuit, storage apparatus, imaging apparatus, and storage control method Dec 6, 2018 Issued
Array ( [id] => 14109565 [patent_doc_number] => 20190096458 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-03-28 [patent_title] => THREE-DIMENSIONAL (3-D) WRITE ASSIST SCHEME FOR MEMORY CELLS [patent_app_type] => utility [patent_app_number] => 16/205534 [patent_app_country] => US [patent_app_date] => 2018-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13466 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16205534 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/205534
Three-dimensional (3-D) write assist scheme for memory cells Nov 29, 2018 Issued
Array ( [id] => 16873293 [patent_doc_number] => 20210166760 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-03 [patent_title] => SEMICONDUCTOR CIRCUIT AND SEMICONDUCTOR CIRCUIT SYSTEM [patent_app_type] => utility [patent_app_number] => 16/768880 [patent_app_country] => US [patent_app_date] => 2018-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 23748 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -26 [patent_words_short_claim] => 229 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16768880 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/768880
Semiconductor circuit and semiconductor circuit system to suppress disturbance in the semiconductor circuit Nov 28, 2018 Issued
Array ( [id] => 15759881 [patent_doc_number] => 10622067 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-04-14 [patent_title] => Memory systems and memory writing methods [patent_app_type] => utility [patent_app_number] => 16/189387 [patent_app_country] => US [patent_app_date] => 2018-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 16 [patent_no_of_words] => 5241 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16189387 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/189387
Memory systems and memory writing methods Nov 12, 2018 Issued
Array ( [id] => 16293299 [patent_doc_number] => 10770152 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-09-08 [patent_title] => Methods of operating a memory device comparing input data to data stored in memory cells coupled to a data line [patent_app_type] => utility [patent_app_number] => 16/180137 [patent_app_country] => US [patent_app_date] => 2018-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 17934 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 327 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16180137 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/180137
Methods of operating a memory device comparing input data to data stored in memory cells coupled to a data line Nov 4, 2018 Issued
Array ( [id] => 14024151 [patent_doc_number] => 20190074069 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-03-07 [patent_title] => METHODS OF OPERATING A MEMORY DEVICE COMPARING INPUT DATA TO DATA STORED IN MEMORY CELLS COUPLED TO A DATA LINE [patent_app_type] => utility [patent_app_number] => 16/180154 [patent_app_country] => US [patent_app_date] => 2018-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17927 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16180154 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/180154
Methods of operating a memory device comparing input data to data stored in memory cells coupled to a data line Nov 4, 2018 Issued
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