Search

Alfredo Bermudez Lozada

Examiner (ID: 7463, Phone: (571)272-0877 , Office: P/2825 )

Most Active Art Unit
2825
Art Unit(s)
2825
Total Applications
617
Issued Applications
490
Pending Applications
86
Abandoned Applications
57

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 14237551 [patent_doc_number] => 20190130948 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-02 [patent_title] => Memory Element [patent_app_type] => utility [patent_app_number] => 15/799171 [patent_app_country] => US [patent_app_date] => 2017-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6323 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15799171 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/799171
Secure memory element for logical state storage Oct 30, 2017 Issued
Array ( [id] => 12716068 [patent_doc_number] => 20180130522 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-10 [patent_title] => TUNABLE NEGATIVE BITLINE WRITE ASSIST AND BOOST ATTENUATION CIRCUIT [patent_app_type] => utility [patent_app_number] => 15/798785 [patent_app_country] => US [patent_app_date] => 2017-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5357 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 333 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15798785 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/798785
Tunable negative bit line write assist and boost attenuation circuit Oct 30, 2017 Issued
Array ( [id] => 14237621 [patent_doc_number] => 20190130983 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-02 [patent_title] => SLC PAGE READ [patent_app_type] => utility [patent_app_number] => 15/799655 [patent_app_country] => US [patent_app_date] => 2017-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14006 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15799655 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/799655
SLC page read Oct 30, 2017 Issued
Array ( [id] => 13976293 [patent_doc_number] => 10217510 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-02-26 [patent_title] => Tunable negative bitline write assist and boost attenuation circuit [patent_app_type] => utility [patent_app_number] => 15/798764 [patent_app_country] => US [patent_app_date] => 2017-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 5356 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 276 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15798764 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/798764
Tunable negative bitline write assist and boost attenuation circuit Oct 30, 2017 Issued
Array ( [id] => 14768609 [patent_doc_number] => 10395705 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-08-27 [patent_title] => Integrated circuit copy prevention device powered by a photoelectric cell [patent_app_type] => utility [patent_app_number] => 15/793046 [patent_app_country] => US [patent_app_date] => 2017-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 3506 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15793046 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/793046
Integrated circuit copy prevention device powered by a photoelectric cell Oct 24, 2017 Issued
Array ( [id] => 12221722 [patent_doc_number] => 20180060082 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-03-01 [patent_title] => 'SYSTEMS AND METHODS INVOLVING CONTROL-I/O BUFFER ENABLE CIRCUITS AND/OR FEATURES OF SAVING POWER IN STANDBY MODE' [patent_app_type] => utility [patent_app_number] => 15/787667 [patent_app_country] => US [patent_app_date] => 2017-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 7846 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15787667 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/787667
Systems and methods involving control-I/O buffer enable circuits and/or features of saving power in standby mode Oct 17, 2017 Issued
Array ( [id] => 12208329 [patent_doc_number] => 20180053555 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-02-22 [patent_title] => 'PROGRAMMING NONVOLATILE MEMORY CELLS USING RESOLUTION-BASED AND LEVEL-BASED VOLTAGE INCREMENTS' [patent_app_type] => utility [patent_app_number] => 15/786402 [patent_app_country] => US [patent_app_date] => 2017-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 21333 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15786402 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/786402
Programming nonvolatile memory cells using resolution-based and level-based voltage increments Oct 16, 2017 Issued
Array ( [id] => 12181433 [patent_doc_number] => 20180040369 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-02-08 [patent_title] => 'PROGRAMMING NONVOLATILE MEMORY CELLS THROUGH A SERIES OF PREDETERMINED THRESHOLD VOLTAGES' [patent_app_type] => utility [patent_app_number] => 15/786339 [patent_app_country] => US [patent_app_date] => 2017-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 21333 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15786339 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/786339
Programming nonvolatile memory cells through a series of predetermined threshold voltages Oct 16, 2017 Issued
Array ( [id] => 14163587 [patent_doc_number] => 20190108896 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-04-11 [patent_title] => SYSTEMS AND METHODS FOR PROVIDING POST-PACKAGE REPAIR VISIBILITY TO A HOST FOR MEMORY RELIABILITY, AVAILABILITY, AND SERVICEABILITY [patent_app_type] => utility [patent_app_number] => 15/726065 [patent_app_country] => US [patent_app_date] => 2017-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3867 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15726065 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/726065
SYSTEMS AND METHODS FOR PROVIDING POST-PACKAGE REPAIR VISIBILITY TO A HOST FOR MEMORY RELIABILITY, AVAILABILITY, AND SERVICEABILITY Oct 4, 2017 Abandoned
Array ( [id] => 13432401 [patent_doc_number] => 20180267743 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-09-20 [patent_title] => ELECTRONIC DEVICE INCLUDING SEMICONDUCTOR MEMORY [patent_app_type] => utility [patent_app_number] => 15/723659 [patent_app_country] => US [patent_app_date] => 2017-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15303 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15723659 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/723659
Electronic device including semiconductor memory having different distances between switching elements and variable resistance elements Oct 2, 2017 Issued
Array ( [id] => 12691942 [patent_doc_number] => 20180122480 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-03 [patent_title] => CONTROL CIRCUIT, SEMICONDUCTOR STORAGE DEVICE, AND METHOD OF CONTROLLING SEMICONDUCTOR STORAGE DEVICE [patent_app_type] => utility [patent_app_number] => 15/718029 [patent_app_country] => US [patent_app_date] => 2017-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6129 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15718029 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/718029
Control circuit, semiconductor storage device, and method of controlling semiconductor storage device Sep 27, 2017 Issued
Array ( [id] => 12129060 [patent_doc_number] => 20180012647 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-01-11 [patent_title] => 'METHODS, APPARATUS AND SYSTEM FOR PROVIDING NMOS-ONLY MEMORY CELLS' [patent_app_type] => utility [patent_app_number] => 15/711714 [patent_app_country] => US [patent_app_date] => 2017-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5750 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15711714 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/711714
METHODS, APPARATUS AND SYSTEM FOR PROVIDING NMOS-ONLY MEMORY CELLS Sep 20, 2017 Abandoned
Array ( [id] => 16803089 [patent_doc_number] => 10998040 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-05-04 [patent_title] => Computational memory cell and processing array device using the memory cells for XOR and XNOR computations [patent_app_type] => utility [patent_app_number] => 15/709399 [patent_app_country] => US [patent_app_date] => 2017-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 6303 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15709399 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/709399
Computational memory cell and processing array device using the memory cells for XOR and XNOR computations Sep 18, 2017 Issued
Array ( [id] => 13878279 [patent_doc_number] => 20190035480 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-01-31 [patent_title] => Non-volatile Memory With Methods To Reduce Creep-Up Field Between Dummy Control Gate And Select Gate [patent_app_type] => utility [patent_app_number] => 15/699513 [patent_app_country] => US [patent_app_date] => 2017-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 20691 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15699513 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/699513
Non-volatile memory with methods to reduce creep-up field between dummy control gate and select gate Sep 7, 2017 Issued
Array ( [id] => 13451367 [patent_doc_number] => 20180277226 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-09-27 [patent_title] => MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 15/698141 [patent_app_country] => US [patent_app_date] => 2017-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 27112 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15698141 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/698141
Multi-bit memory system with adaptive read voltage controller Sep 6, 2017 Issued
Array ( [id] => 13451363 [patent_doc_number] => 20180277224 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-09-27 [patent_title] => MEMORY DEVICE AND INFORMATION PROCESSING SYSTEM [patent_app_type] => utility [patent_app_number] => 15/695563 [patent_app_country] => US [patent_app_date] => 2017-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17140 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15695563 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/695563
Memory device and information processing system Sep 4, 2017 Issued
Array ( [id] => 13708695 [patent_doc_number] => 20170365302 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-12-21 [patent_title] => LATCHING CURRENT SENSING AMPLIFIER FOR MEMORY ARRAY [patent_app_type] => utility [patent_app_number] => 15/695457 [patent_app_country] => US [patent_app_date] => 2017-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2950 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15695457 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/695457
Latching current sensing amplifier for memory array Sep 4, 2017 Issued
Array ( [id] => 13320339 [patent_doc_number] => 20180211707 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-07-26 [patent_title] => SEMICONDUCTOR MEMORY DEVICE AND METHOD OF CONTROLLING SEMICONDUCTOR MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 15/694975 [patent_app_country] => US [patent_app_date] => 2017-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8392 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 43 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15694975 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/694975
SEMICONDUCTOR MEMORY DEVICE AND METHOD OF CONTROLLING SEMICONDUCTOR MEMORY DEVICE Sep 3, 2017 Abandoned
Array ( [id] => 13419465 [patent_doc_number] => 20180261275 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-09-13 [patent_title] => MEMORY SYSTEM THAT DIFFERENTIATES VOLTAGES APPLIED TO WORD LINES [patent_app_type] => utility [patent_app_number] => 15/687103 [patent_app_country] => US [patent_app_date] => 2017-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17031 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15687103 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/687103
Memory system that differentiates voltages applied to word lines Aug 24, 2017 Issued
Array ( [id] => 13995191 [patent_doc_number] => 20190066753 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-02-28 [patent_title] => SELF-REFERENCING MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 15/687019 [patent_app_country] => US [patent_app_date] => 2017-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18084 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15687019 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/687019
Self-referencing memory device Aug 24, 2017 Issued
Menu