Search

Alfredo Bermudez Lozada

Examiner (ID: 7463, Phone: (571)272-0877 , Office: P/2825 )

Most Active Art Unit
2825
Art Unit(s)
2825
Total Applications
617
Issued Applications
490
Pending Applications
86
Abandoned Applications
57

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 13995161 [patent_doc_number] => 20190066738 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-02-28 [patent_title] => SEMICONDUCTOR DIES SUPPORTING MULTIPLE PACKAGING CONFIGURATIONS AND ASSOCIATED METHODS [patent_app_type] => utility [patent_app_number] => 15/684577 [patent_app_country] => US [patent_app_date] => 2017-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4419 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15684577 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/684577
Semiconductor dies supporting multiple packaging configurations and associated methods Aug 22, 2017 Issued
Array ( [id] => 13991843 [patent_doc_number] => 20190065079 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-02-28 [patent_title] => SYSTEM AND METHOD FOR PRESERVING DATA IN VOLATILE MEMORY [patent_app_type] => utility [patent_app_number] => 15/683793 [patent_app_country] => US [patent_app_date] => 2017-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2934 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15683793 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/683793
System and method for preserving data in volatile memory Aug 22, 2017 Issued
Array ( [id] => 12208310 [patent_doc_number] => 20180053535 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-02-22 [patent_title] => 'MEMORY DEVICE AND CENTRAL PROCESSING UNIT' [patent_app_type] => utility [patent_app_number] => 15/681885 [patent_app_country] => US [patent_app_date] => 2017-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 9317 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15681885 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/681885
Memory device including error detection circuit Aug 20, 2017 Issued
Array ( [id] => 12822835 [patent_doc_number] => 20180166117 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-06-14 [patent_title] => MEMROY DEVICE AND OPERATING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 15/681595 [patent_app_country] => US [patent_app_date] => 2017-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12570 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 45 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15681595 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/681595
MEMROY DEVICE AND OPERATING METHOD THEREOF Aug 20, 2017 Abandoned
Array ( [id] => 12263544 [patent_doc_number] => 20180082740 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-03-22 [patent_title] => 'RESISTANCE VARIABLE MEMORY APPARATUS' [patent_app_type] => utility [patent_app_number] => 15/681151 [patent_app_country] => US [patent_app_date] => 2017-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4656 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15681151 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/681151
Resistance variable memory apparatus Aug 17, 2017 Issued
Array ( [id] => 13962781 [patent_doc_number] => 20190057735 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-02-21 [patent_title] => Self-Timing Path with Substrate-Connected Dummy Bitline [patent_app_type] => utility [patent_app_number] => 15/679325 [patent_app_country] => US [patent_app_date] => 2017-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3974 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15679325 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/679325
Dummy bitline circuitry Aug 16, 2017 Issued
Array ( [id] => 13976307 [patent_doc_number] => 10217518 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-02-26 [patent_title] => Reducing hot electron injection type of read disturb in 3D memory device having connected source-end select gates [patent_app_type] => utility [patent_app_number] => 15/678683 [patent_app_country] => US [patent_app_date] => 2017-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 39 [patent_no_of_words] => 19598 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 247 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15678683 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/678683
Reducing hot electron injection type of read disturb in 3D memory device having connected source-end select gates Aug 15, 2017 Issued
Array ( [id] => 12181448 [patent_doc_number] => 20180040384 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-02-08 [patent_title] => 'MULTIPLE TEMPERATURE TESTING OF NON-VOLATILE MEMORY DATA RETENTION TIME' [patent_app_type] => utility [patent_app_number] => 15/672171 [patent_app_country] => US [patent_app_date] => 2017-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3792 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15672171 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/672171
MULTIPLE TEMPERATURE TESTING OF NON-VOLATILE MEMORY DATA RETENTION TIME Aug 7, 2017 Abandoned
Array ( [id] => 14491615 [patent_doc_number] => 10332605 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-06-25 [patent_title] => Methods of operating a memory device comparing input data to data stored in memory cells coupled to a data line [patent_app_type] => utility [patent_app_number] => 15/645009 [patent_app_country] => US [patent_app_date] => 2017-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 17892 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15645009 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/645009
Methods of operating a memory device comparing input data to data stored in memory cells coupled to a data line Jul 9, 2017 Issued
Array ( [id] => 14332537 [patent_doc_number] => 10297292 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-05-21 [patent_title] => Sense structure based on multiple sense amplifiers with local regulation of a biasing voltage [patent_app_type] => utility [patent_app_number] => 15/620325 [patent_app_country] => US [patent_app_date] => 2017-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6714 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15620325 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/620325
Sense structure based on multiple sense amplifiers with local regulation of a biasing voltage Jun 11, 2017 Issued
Array ( [id] => 12665341 [patent_doc_number] => 20180113613 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-04-26 [patent_title] => INFORMATION RECEIVING DEVICE AND SEMICONDUCTOR DEVICE INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 15/584791 [patent_app_country] => US [patent_app_date] => 2017-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4513 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15584791 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/584791
INFORMATION RECEIVING DEVICE AND SEMICONDUCTOR DEVICE INCLUDING THE SAME May 1, 2017 Abandoned
Array ( [id] => 13228385 [patent_doc_number] => 10127971 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-11-13 [patent_title] => Systems and methods for memory cell array initialization [patent_app_type] => utility [patent_app_number] => 15/583023 [patent_app_country] => US [patent_app_date] => 2017-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6357 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15583023 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/583023
Systems and methods for memory cell array initialization Apr 30, 2017 Issued
Array ( [id] => 12223130 [patent_doc_number] => 20180061491 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-03-01 [patent_title] => 'SEMICONDUCTOR SYSTEM INCLUDING A PHASE CHANGEABLE MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 15/581885 [patent_app_country] => US [patent_app_date] => 2017-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4989 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15581885 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/581885
Semiconductor system including a phase changeable memory device Apr 27, 2017 Issued
Array ( [id] => 14252041 [patent_doc_number] => 10276227 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-04-30 [patent_title] => Write algorithm for memory to reduce failure rate of write operations [patent_app_type] => utility [patent_app_number] => 15/581097 [patent_app_country] => US [patent_app_date] => 2017-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4369 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15581097 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/581097
Write algorithm for memory to reduce failure rate of write operations Apr 27, 2017 Issued
Array ( [id] => 13173595 [patent_doc_number] => 10102917 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-10-16 [patent_title] => Multi-bit-per-cell three-dimensional one-time-programmable memory [patent_app_type] => utility [patent_app_number] => 15/488435 [patent_app_country] => US [patent_app_date] => 2017-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 19 [patent_no_of_words] => 4174 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15488435 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/488435
Multi-bit-per-cell three-dimensional one-time-programmable memory Apr 13, 2017 Issued
Array ( [id] => 13934373 [patent_doc_number] => 20190050702 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-02-14 [patent_title] => SECURE SEMICONDUCTOR CHIP AND OPERATING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 16/076473 [patent_app_country] => US [patent_app_date] => 2017-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5752 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16076473 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/076473
Secure semiconductor chip and operating method thereof Feb 9, 2017 Issued
Array ( [id] => 15388425 [patent_doc_number] => 10535407 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-01-14 [patent_title] => Adaptive parallel writing to nonvolatile memory cells [patent_app_type] => utility [patent_app_number] => 15/403091 [patent_app_country] => US [patent_app_date] => 2017-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 31 [patent_no_of_words] => 20396 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 270 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15403091 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/403091
Adaptive parallel writing to nonvolatile memory cells Jan 9, 2017 Issued
Array ( [id] => 15388429 [patent_doc_number] => 10535409 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-01-14 [patent_title] => Method for suppressing gate oxide tunnel current in non-volatile memory to reduce disturbs [patent_app_type] => utility [patent_app_number] => 15/394095 [patent_app_country] => US [patent_app_date] => 2016-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 7633 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15394095 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/394095
Method for suppressing gate oxide tunnel current in non-volatile memory to reduce disturbs Dec 28, 2016 Issued
Array ( [id] => 12263545 [patent_doc_number] => 20180082741 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-03-22 [patent_title] => 'RESISTIVE MEMORY APPARATUS AND LINE SELECTION CIRCUIT THEREOF' [patent_app_type] => utility [patent_app_number] => 15/385067 [patent_app_country] => US [patent_app_date] => 2016-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5705 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15385067 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/385067
RESISTIVE MEMORY APPARATUS AND LINE SELECTION CIRCUIT THEREOF Dec 19, 2016 Abandoned
Array ( [id] => 12848350 [patent_doc_number] => 20180174623 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-06-21 [patent_title] => APPARATUS AND METHOD FOR TRANSFERRING DATA BETWEEN DIFFERENT VOLTAGE-CLOCK DOMAINS USING MULTIPLE WRITE-SIDE MULTIPLEXERS [patent_app_type] => utility [patent_app_number] => 15/381587 [patent_app_country] => US [patent_app_date] => 2016-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9853 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -27 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15381587 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/381587
APPARATUS AND METHOD FOR TRANSFERRING DATA BETWEEN DIFFERENT VOLTAGE-CLOCK DOMAINS USING MULTIPLE WRITE-SIDE MULTIPLEXERS Dec 15, 2016 Abandoned
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