
Alfredo Bermudez Lozada
Examiner (ID: 7463, Phone: (571)272-0877 , Office: P/2825 )
| Most Active Art Unit | 2825 |
| Art Unit(s) | 2825 |
| Total Applications | 617 |
| Issued Applications | 490 |
| Pending Applications | 86 |
| Abandoned Applications | 57 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 11571531
[patent_doc_number] => 20170110175
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-04-20
[patent_title] => 'CLEAN DATA STROBE SIGNAL GENERATING CIRCUIT IN READ INTERFACE DEVICE'
[patent_app_type] => utility
[patent_app_number] => 15/292834
[patent_app_country] => US
[patent_app_date] => 2016-10-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 14
[patent_no_of_words] => 11425
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15292834
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/292834 | Clean data strobe signal generating circuit in read interface device | Oct 12, 2016 | Issued |
Array
(
[id] => 14706673
[patent_doc_number] => 10381094
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-08-13
[patent_title] => 3D memory with staged-level multibit programming
[patent_app_type] => utility
[patent_app_number] => 15/290376
[patent_app_country] => US
[patent_app_date] => 2016-10-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 36
[patent_no_of_words] => 7971
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 251
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15290376
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/290376 | 3D memory with staged-level multibit programming | Oct 10, 2016 | Issued |
Array
(
[id] => 12223143
[patent_doc_number] => 20180061503
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-03-01
[patent_title] => 'MEMORY DEVICE AND PROGRAMMING METHOD THEREOF'
[patent_app_type] => utility
[patent_app_number] => 15/288785
[patent_app_country] => US
[patent_app_date] => 2016-10-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 7163
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15288785
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/288785 | Programming method for reducing a width of a threshold voltage distribution curve of memory cells | Oct 6, 2016 | Issued |
Array
(
[id] => 12033579
[patent_doc_number] => 20170323678
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-11-09
[patent_title] => 'DATA OUTPUT CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME'
[patent_app_type] => utility
[patent_app_number] => 15/280005
[patent_app_country] => US
[patent_app_date] => 2016-09-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 9525
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15280005
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/280005 | Data output circuit and semiconductor memory device including the same | Sep 28, 2016 | Issued |
Array
(
[id] => 11366895
[patent_doc_number] => 20170004876
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-01-05
[patent_title] => 'TUNABLE NEGATIVE BITLINE WRITE ASSIST AND BOOST ATTENUATION CIRCUIT'
[patent_app_type] => utility
[patent_app_number] => 15/266343
[patent_app_country] => US
[patent_app_date] => 2016-09-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 5534
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15266343
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/266343 | Tunable negative bitline write assist and boost attenuation circuit | Sep 14, 2016 | Issued |
Array
(
[id] => 13187611
[patent_doc_number] => 10109331
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2018-10-23
[patent_title] => Magnetic storage device with a wiring having a ferromagnetic layer
[patent_app_type] => utility
[patent_app_number] => 15/261815
[patent_app_country] => US
[patent_app_date] => 2016-09-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 20
[patent_figures_cnt] => 20
[patent_no_of_words] => 10933
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 265
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15261815
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/261815 | Magnetic storage device with a wiring having a ferromagnetic layer | Sep 8, 2016 | Issued |
Array
(
[id] => 12223145
[patent_doc_number] => 20180061505
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-03-01
[patent_title] => 'Leakage Current Detection In 3D Memory'
[patent_app_type] => utility
[patent_app_number] => 15/246309
[patent_app_country] => US
[patent_app_date] => 2016-08-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 17
[patent_no_of_words] => 16833
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15246309
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/246309 | Leakage current detection in 3D memory | Aug 23, 2016 | Issued |
Array
(
[id] => 11710881
[patent_doc_number] => 20170179380
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-06-22
[patent_title] => 'MAGNETIC TUNNEL JUNCTION BASED ANTI-FUSES WITH CASCODED TRANSISTORS'
[patent_app_type] => utility
[patent_app_number] => 15/231168
[patent_app_country] => US
[patent_app_date] => 2016-08-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 4385
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15231168
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/231168 | Magnetic tunnel junction based anti-fuses with cascoded transistors | Aug 7, 2016 | Issued |
Array
(
[id] => 12181653
[patent_doc_number] => 20180040589
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-02-08
[patent_title] => 'MICROELECTRONIC PACKAGES AND ASSEMBLIES WITH REPEATERS'
[patent_app_type] => utility
[patent_app_number] => 15/227361
[patent_app_country] => US
[patent_app_date] => 2016-08-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 6766
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15227361
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/227361 | MICROELECTRONIC PACKAGES AND ASSEMBLIES WITH REPEATERS | Aug 2, 2016 | Abandoned |
Array
(
[id] => 13320321
[patent_doc_number] => 20180211698
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-07-26
[patent_title] => A Low Power Decoder Using Resonant Drive Circuitry
[patent_app_type] => utility
[patent_app_number] => 15/746553
[patent_app_country] => US
[patent_app_date] => 2016-07-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5706
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -10
[patent_words_short_claim] => 70
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15746553
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/746553 | Low power decoder using resonant drive circuitry | Jul 25, 2016 | Issued |
Array
(
[id] => 12129050
[patent_doc_number] => 20180012636
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-01-11
[patent_title] => 'SCAN CHAIN OPERATION IN SENSING CIRCUITRY'
[patent_app_type] => utility
[patent_app_number] => 15/205885
[patent_app_country] => US
[patent_app_date] => 2016-07-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 14041
[patent_no_of_claims] => 26
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15205885
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/205885 | Scan chain operation in sensing circuitry | Jul 7, 2016 | Issued |
Array
(
[id] => 13292931
[patent_doc_number] => 10157664
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2018-12-18
[patent_title] => Memory controlling device by using multi-phase control signal and method thereof
[patent_app_type] => utility
[patent_app_number] => 15/190623
[patent_app_country] => US
[patent_app_date] => 2016-06-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 5209
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 225
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15190623
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/190623 | Memory controlling device by using multi-phase control signal and method thereof | Jun 22, 2016 | Issued |
Array
(
[id] => 12395673
[patent_doc_number] => 09966143
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2018-05-08
[patent_title] => Solid state drive with improved power efficiency
[patent_app_type] => utility
[patent_app_number] => 15/173945
[patent_app_country] => US
[patent_app_date] => 2016-06-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 6471
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 151
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15173945
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/173945 | Solid state drive with improved power efficiency | Jun 5, 2016 | Issued |
Array
(
[id] => 12095337
[patent_doc_number] => 20170352430
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-12-07
[patent_title] => 'NON-VOLATILE MEMORY WITH CUSTOMIZED CONTROL OF INJECTION TYPE OF DISTURB DURING PROGRAM VERIFY FOR IMPROVED PROGRAM PERFORMANCE'
[patent_app_type] => utility
[patent_app_number] => 15/172653
[patent_app_country] => US
[patent_app_date] => 2016-06-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 16
[patent_no_of_words] => 16091
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15172653
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/172653 | Non-volatile memory with customized control of injection type of disturb during program verify for improved program performance | Jun 2, 2016 | Issued |
Array
(
[id] => 11932392
[patent_doc_number] => 09799393
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2017-10-24
[patent_title] => 'Methods, apparatus and system for providing NMOS-only memory cells'
[patent_app_type] => utility
[patent_app_number] => 15/169342
[patent_app_country] => US
[patent_app_date] => 2016-05-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 5750
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 172
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15169342
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/169342 | Methods, apparatus and system for providing NMOS-only memory cells | May 30, 2016 | Issued |
Array
(
[id] => 12935233
[patent_doc_number] => 09830963
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2017-11-28
[patent_title] => Word line-dependent and temperature-dependent erase depth
[patent_app_type] => utility
[patent_app_number] => 15/163171
[patent_app_country] => US
[patent_app_date] => 2016-05-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 29
[patent_figures_cnt] => 54
[patent_no_of_words] => 18427
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 142
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15163171
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/163171 | Word line-dependent and temperature-dependent erase depth | May 23, 2016 | Issued |
Array
(
[id] => 11071014
[patent_doc_number] => 20160267978
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-09-15
[patent_title] => 'Memory Devices and Memory Operational Methods'
[patent_app_type] => utility
[patent_app_number] => 15/162420
[patent_app_country] => US
[patent_app_date] => 2016-05-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 15
[patent_no_of_words] => 5327
[patent_no_of_claims] => 33
[patent_no_of_ind_claims] => 7
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15162420
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/162420 | Memory devices and methods of writing memory cells at different moments in time | May 22, 2016 | Issued |
Array
(
[id] => 13754433
[patent_doc_number] => 10170167
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-01-01
[patent_title] => Single node power management for multiple memory devices
[patent_app_type] => utility
[patent_app_number] => 15/162128
[patent_app_country] => US
[patent_app_date] => 2016-05-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 8938
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 167
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15162128
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/162128 | Single node power management for multiple memory devices | May 22, 2016 | Issued |
Array
(
[id] => 12114831
[patent_doc_number] => 09870826
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2018-01-16
[patent_title] => 'Memory apparatus and data access method thereof by using multiple memories for lifetime extension'
[patent_app_type] => utility
[patent_app_number] => 15/152581
[patent_app_country] => US
[patent_app_date] => 2016-05-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 7
[patent_no_of_words] => 6760
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 379
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15152581
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/152581 | Memory apparatus and data access method thereof by using multiple memories for lifetime extension | May 11, 2016 | Issued |
Array
(
[id] => 12026725
[patent_doc_number] => 20170316824
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-11-02
[patent_title] => 'MULTI-LAYER RESISTIVE MEMORY DEVICES'
[patent_app_type] => utility
[patent_app_number] => 15/143349
[patent_app_country] => US
[patent_app_date] => 2016-04-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 13
[patent_no_of_words] => 5976
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15143349
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/143349 | MULTI-LAYER RESISTIVE MEMORY DEVICES | Apr 28, 2016 | Abandoned |