Search

Alfredo Bermudez Lozada

Examiner (ID: 7463, Phone: (571)272-0877 , Office: P/2825 )

Most Active Art Unit
2825
Art Unit(s)
2825
Total Applications
617
Issued Applications
490
Pending Applications
86
Abandoned Applications
57

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 12005167 [patent_doc_number] => 20170309322 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-10-26 [patent_title] => 'Memory Arrays, Ferroelectric Transistors, and Methods of Reading and Writing Relative to Memory Cells of Memory Arrays' [patent_app_type] => utility [patent_app_number] => 15/134221 [patent_app_country] => US [patent_app_date] => 2016-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5991 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15134221 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/134221
Memory arrays, ferroelectric transistors, and methods of reading and writing relative to memory cells of memory arrays Apr 19, 2016 Issued
Array ( [id] => 11036010 [patent_doc_number] => 20160232966 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-08-11 [patent_title] => 'TUNABLE NEGATIVE BITLINE WRITE ASSIST AND BOOST ATTENUATION CIRCUIT' [patent_app_type] => utility [patent_app_number] => 15/097703 [patent_app_country] => US [patent_app_date] => 2016-04-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5529 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15097703 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/097703
Tunable negative bitline write assist and boost attenuation circuit Apr 12, 2016 Issued
Array ( [id] => 15547147 [patent_doc_number] => 10573363 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-02-25 [patent_title] => Method and apparatus for performing self-referenced read in a magnetoresistive random access memory [patent_app_type] => utility [patent_app_number] => 15/087939 [patent_app_country] => US [patent_app_date] => 2016-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5951 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15087939 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/087939
Method and apparatus for performing self-referenced read in a magnetoresistive random access memory Mar 30, 2016 Issued
Array ( [id] => 11020901 [patent_doc_number] => 20160217856 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-07-28 [patent_title] => 'METHOD AND CIRCUIT FOR SWITCHING A MEMRISTIVE DEVICE' [patent_app_type] => utility [patent_app_number] => 15/085403 [patent_app_country] => US [patent_app_date] => 2016-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4277 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15085403 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/085403
METHOD AND CIRCUIT FOR SWITCHING A MEMRISTIVE DEVICE Mar 29, 2016 Abandoned
Array ( [id] => 14267223 [patent_doc_number] => 10283181 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-05-07 [patent_title] => Time tracking circuit for FRAM [patent_app_type] => utility [patent_app_number] => 15/057475 [patent_app_country] => US [patent_app_date] => 2016-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 8624 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 262 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15057475 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/057475
Time tracking circuit for FRAM Feb 29, 2016 Issued
Array ( [id] => 12208318 [patent_doc_number] => 20180053544 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-02-22 [patent_title] => 'MEMORIES AND MEMORY COMPONENTS WITH INTERCONNECTED AND REDUNDANT DATA INTERFACES' [patent_app_type] => utility [patent_app_number] => 15/552569 [patent_app_country] => US [patent_app_date] => 2016-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 10678 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15552569 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/552569
Memories and memory components with interconnected and redundant data interfaces Feb 21, 2016 Issued
Array ( [id] => 11607769 [patent_doc_number] => 20170125072 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-05-04 [patent_title] => 'SEMICONDUCTOR APPARATUS' [patent_app_type] => utility [patent_app_number] => 15/048529 [patent_app_country] => US [patent_app_date] => 2016-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3630 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15048529 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/048529
Semiconductor apparatus capable of improving efficiency for a circuit configuration and a signal line interconnection Feb 18, 2016 Issued
Array ( [id] => 11643742 [patent_doc_number] => 09665115 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-05-30 [patent_title] => 'Reconfigurable power distribution system for three-dimensional integrated circuits' [patent_app_type] => utility [patent_app_number] => 15/042751 [patent_app_country] => US [patent_app_date] => 2016-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3701 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 272 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15042751 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/042751
Reconfigurable power distribution system for three-dimensional integrated circuits Feb 11, 2016 Issued
Array ( [id] => 10786183 [patent_doc_number] => 20160132339 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-05-12 [patent_title] => 'SYSTEMS AND METHODS INVOLVING CONTROL-I/O BUFFER ENABLE CIRCUITS AND/OR FEATURES OF SAVING POWER IN STANDBY MODE' [patent_app_type] => utility [patent_app_number] => 14/996870 [patent_app_country] => US [patent_app_date] => 2016-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 7793 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14996870 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/996870
Systems and methods involving control-I/O buffer enable circuits and/or features of saving power in standby mode Jan 14, 2016 Issued
Array ( [id] => 11360269 [patent_doc_number] => 09536926 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-01-03 [patent_title] => 'Magnetic tunnel junction based anti-fuses with cascoded transistors' [patent_app_type] => utility [patent_app_number] => 14/978013 [patent_app_country] => US [patent_app_date] => 2015-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 4413 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14978013 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/978013
Magnetic tunnel junction based anti-fuses with cascoded transistors Dec 21, 2015 Issued
Array ( [id] => 13214319 [patent_doc_number] => 10121534 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-11-06 [patent_title] => Integrated circuit with overdriven and underdriven pass gates [patent_app_type] => utility [patent_app_number] => 14/974015 [patent_app_country] => US [patent_app_date] => 2015-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6858 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14974015 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/974015
Integrated circuit with overdriven and underdriven pass gates Dec 17, 2015 Issued
Array ( [id] => 11517280 [patent_doc_number] => 20170084353 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-23 [patent_title] => 'SEMICONDUCTOR DEVICE FOR PERFORMING REPAIR OPERATIONS' [patent_app_type] => utility [patent_app_number] => 14/975275 [patent_app_country] => US [patent_app_date] => 2015-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8676 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14975275 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/975275
Semiconductor device for performing repair operations Dec 17, 2015 Issued
Array ( [id] => 10984306 [patent_doc_number] => 20160181251 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-06-23 [patent_title] => 'SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 14/973649 [patent_app_country] => US [patent_app_date] => 2015-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 12660 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14973649 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/973649
Semiconductor device with two transistors and a capacitor Dec 16, 2015 Issued
Array ( [id] => 10825870 [patent_doc_number] => 20160172037 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-06-16 [patent_title] => 'NOVEL LV NAND-CAM SEARCH SCHEME USING EXISTING CIRCUITS WITH LEAST OVERHEAD' [patent_app_type] => utility [patent_app_number] => 14/970525 [patent_app_country] => US [patent_app_date] => 2015-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 47 [patent_figures_cnt] => 47 [patent_no_of_words] => 41499 [patent_no_of_claims] => 72 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14970525 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/970525
NOVEL LV NAND-CAM SEARCH SCHEME USING EXISTING CIRCUITS WITH LEAST OVERHEAD Dec 14, 2015 Abandoned
Array ( [id] => 14919961 [patent_doc_number] => 10431307 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-10-01 [patent_title] => Array organization and architecture to perform range-match operations with content addressable memory (CAM) circuits [patent_app_type] => utility [patent_app_number] => 14/962350 [patent_app_country] => US [patent_app_date] => 2015-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 4703 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 343 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14962350 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/962350
Array organization and architecture to perform range-match operations with content addressable memory (CAM) circuits Dec 7, 2015 Issued
Array ( [id] => 10740505 [patent_doc_number] => 20160086656 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-03-24 [patent_title] => 'Semiconductor Device Having Memory Cell With Electrostatic Capacitance Circuit' [patent_app_type] => utility [patent_app_number] => 14/960510 [patent_app_country] => US [patent_app_date] => 2015-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 10903 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14960510 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/960510
Semiconductor Device Having Memory Cell With Electrostatic Capacitance Circuit Dec 6, 2015 Abandoned
Array ( [id] => 11057095 [patent_doc_number] => 20160254057 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-09-01 [patent_title] => 'SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 14/957389 [patent_app_country] => US [patent_app_date] => 2015-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 11918 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14957389 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/957389
Semiconductor device including boosted voltage supply circuit for supplying boosted voltage to memory array Dec 1, 2015 Issued
Array ( [id] => 10717947 [patent_doc_number] => 20160064094 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-03-03 [patent_title] => 'NONCONSECUTIVE SENSING OF MULTILEVEL MEMORY CELLS' [patent_app_type] => utility [patent_app_number] => 14/935744 [patent_app_country] => US [patent_app_date] => 2015-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8361 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14935744 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/935744
Nonconsecutive sensing of multilevel memory cells Nov 8, 2015 Issued
Array ( [id] => 14397913 [patent_doc_number] => 10312248 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-06-04 [patent_title] => Virtual ground non-volatile memory array [patent_app_type] => utility [patent_app_number] => 14/935201 [patent_app_country] => US [patent_app_date] => 2015-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 32 [patent_no_of_words] => 6034 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 459 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14935201 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/935201
Virtual ground non-volatile memory array Nov 5, 2015 Issued
Array ( [id] => 11753175 [patent_doc_number] => 09711192 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-07-18 [patent_title] => 'Memory device having different data-size access modes for different power modes' [patent_app_type] => utility [patent_app_number] => 14/931291 [patent_app_country] => US [patent_app_date] => 2015-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 9795 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14931291 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/931291
Memory device having different data-size access modes for different power modes Nov 2, 2015 Issued
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