Alfredo Bermudez Lozada

Array ( [id] => 12553524 [patent_doc_number] => 10014063 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-07-03 [patent_title] => Smart skip verify mode for programming a memory device [patent_app_type] => utility [patent_app_number] => 14/928853 [patent_app_country] => US [patent_app_date] => 2015-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 49 [patent_no_of_words] => 16312 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14928853 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11117869 [patent_doc_number] => 20160314844 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-10-27 [patent_title] => 'NATURAL THRESHOLD VOLTAGE COMPACTION WITH DUAL PULSE PROGRAM FOR NON-VOLATILE MEMORY' [patent_app_type] => utility [patent_app_number] => 14/926167 [patent_app_country] => US [patent_app_date] => 2015-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 19493 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14926167 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12534225 [patent_doc_number] => 10008265 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-06-26 [patent_title] => Method and apparatus for providing three-dimensional integrated nonvolatile memory (NVM) and dynamic random access memory (DRAM) memory device [patent_app_type] => utility [patent_app_number] => 14/923247 [patent_app_country] => US [patent_app_date] => 2015-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 50 [patent_no_of_words] => 8959 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14923247 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11326219 [patent_doc_number] => 20160356830 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-12-08 [patent_title] => 'METHOD, SYSTEM, USER TERMINAL AND APPARATUS FOR POWER MANAGEMENT' [patent_app_type] => utility [patent_app_number] => 14/862192 [patent_app_country] => US [patent_app_date] => 2015-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 10030 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14862192 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14702813 [patent_doc_number] => 10379146 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-08-13 [patent_title] => Detecting non-technical losses in electrical networks based on multi-layered statistical techniques from smart meter data [patent_app_type] => utility [patent_app_number] => 14/862487 [patent_app_country] => US [patent_app_date] => 2015-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6591 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 350 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14862487 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11502617 [patent_doc_number] => 20170076802 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-16 [patent_title] => 'Programming of Nonvolatile Memory with Verify Level Dependent on Memory State and Programming Loop Count' [patent_app_type] => utility [patent_app_number] => 14/853733 [patent_app_country] => US [patent_app_date] => 2015-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 9397 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14853733 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15488001 [patent_doc_number] => 10559355 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-02-11 [patent_title] => Device and method for writing data to a resistive memory [patent_app_type] => utility [patent_app_number] => 14/848265 [patent_app_country] => US [patent_app_date] => 2015-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 18 [patent_no_of_words] => 11038 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 229 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14848265 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14093661 [patent_doc_number] => 10242743 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-03-26 [patent_title] => Method and apparatus for writing nonvolatile memory using multiple-page programming [patent_app_type] => utility [patent_app_number] => 14/846673 [patent_app_country] => US [patent_app_date] => 2015-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 17 [patent_no_of_words] => 9539 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14846673 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14734817 [patent_doc_number] => 10386806 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-08-20 [patent_title] => Method for connecting models of technical systems in a testing device equipped for control unit development [patent_app_type] => utility [patent_app_number] => 14/842152 [patent_app_country] => US [patent_app_date] => 2015-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 16071 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 522 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14842152 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11063532 [patent_doc_number] => 20160260494 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-09-08 [patent_title] => 'ACCESS APPARATUS OF MEMORY CARD AND CONTROL METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 14/805409 [patent_app_country] => US [patent_app_date] => 2015-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5606 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14805409 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10433035 [patent_doc_number] => 20150318047 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-11-05 [patent_title] => 'MEMORY DEVICES CONFIGURED TO APPLY DIFFERENT WEIGHTS TO DIFFERENT STRINGS OF MEMORY CELLS COUPLED TO A DATA LINE AND METHODS' [patent_app_type] => utility [patent_app_number] => 14/798845 [patent_app_country] => US [patent_app_date] => 2015-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 20094 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14798845 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10425900 [patent_doc_number] => 20150310911 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-10-29 [patent_title] => 'DETERMINING WHETHER A MEMORY CELL STATE IS IN A VALLEY BETWEEN ADJACENT DATA STATES' [patent_app_type] => utility [patent_app_number] => 14/735312 [patent_app_country] => US [patent_app_date] => 2015-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7691 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14735312 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12162203 [patent_doc_number] => 20180033469 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-02-01 [patent_title] => 'MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 15/552813 [patent_app_country] => US [patent_app_date] => 2015-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 11812 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15552813 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14252031 [patent_doc_number] => 10276222 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-04-30 [patent_title] => Method for accessing a memory and memory access circuit [patent_app_type] => utility [patent_app_number] => 14/710617 [patent_app_country] => US [patent_app_date] => 2015-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5526 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14710617 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11271733 [patent_doc_number] => 20160334280 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-11-17 [patent_title] => 'ONLINE IGBT JUNCTION TEMPERATURE ESTIMATION WITHOUT THE USE OF A DEDICATED TEMPERATURE ESTIMATION OR MEASUREMENT DEVICE' [patent_app_type] => utility [patent_app_number] => 14/709782 [patent_app_country] => US [patent_app_date] => 2015-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5313 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14709782 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13270779 [patent_doc_number] => 10147476 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-12-04 [patent_title] => Semiconductor device, semiconductor system with the semiconductor device and method of driving the semiconductor system capable of performing refresh operations in units of groups of semiconductor devices [patent_app_type] => utility [patent_app_number] => 14/709143 [patent_app_country] => US [patent_app_date] => 2015-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4646 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 304 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14709143 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11132131 [patent_doc_number] => 20160329106 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-11-10 [patent_title] => 'INPUT/OUTPUT INTERFACE CIRCUITS AND METHODS FOR MEMORY DEVICES' [patent_app_type] => utility [patent_app_number] => 14/706195 [patent_app_country] => US [patent_app_date] => 2015-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 31 [patent_no_of_words] => 11903 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14706195 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11020892 [patent_doc_number] => 20160217846 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-07-28 [patent_title] => 'SEMICONDUCTOR DEVICES CONFIGURED TO GENERATE A BANK ACTIVE SIGNAL' [patent_app_type] => utility [patent_app_number] => 14/705157 [patent_app_country] => US [patent_app_date] => 2015-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4537 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14705157 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10447724 [patent_doc_number] => 20150332739 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-11-19 [patent_title] => 'SENSE STRUCTURE BASED ON MULTIPLE SENSE AMPLIFIERS WITH LOCAL REGULATION OF A BIASING VOLTAGE' [patent_app_type] => utility [patent_app_number] => 14/703173 [patent_app_country] => US [patent_app_date] => 2015-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6901 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14703173 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11807043 [patent_doc_number] => 09548125 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-01-17 [patent_title] => 'Semiconductor device having multi-level cell and method of reading the same' [patent_app_type] => utility [patent_app_number] => 14/702951 [patent_app_country] => US [patent_app_date] => 2015-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 4805 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 233 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14702951 [rel_patent_id] =>[rel_patent_doc_number] =>)