Search

Alfredo Bermudez Lozada

Examiner (ID: 7463, Phone: (571)272-0877 , Office: P/2825 )

Most Active Art Unit
2825
Art Unit(s)
2825
Total Applications
617
Issued Applications
490
Pending Applications
86
Abandoned Applications
57

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 12515589 [patent_doc_number] => 10002664 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-06-19 [patent_title] => Non-volatile resistive memory cell comprising metal electrodes and a solid electrolyte between the metal electrodes [patent_app_type] => utility [patent_app_number] => 14/489789 [patent_app_country] => US [patent_app_date] => 2014-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 11 [patent_no_of_words] => 6819 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 365 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14489789 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/489789
Non-volatile resistive memory cell comprising metal electrodes and a solid electrolyte between the metal electrodes Sep 17, 2014 Issued
Array ( [id] => 10447728 [patent_doc_number] => 20150332742 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-11-19 [patent_title] => 'SEMICONDUCTOR MEMORY APPARATUS' [patent_app_type] => utility [patent_app_number] => 14/488521 [patent_app_country] => US [patent_app_date] => 2014-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8076 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14488521 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/488521
Semiconductor memory apparatus converting serial type data into parallel type data in response to pipe control signals and pipe control signals during a training operation Sep 16, 2014 Issued
Array ( [id] => 10590383 [patent_doc_number] => 09312003 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-04-12 [patent_title] => 'Semiconductor memory device and method of performing setting operation in semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 14/487607 [patent_app_country] => US [patent_app_date] => 2014-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 38 [patent_no_of_words] => 9948 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14487607 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/487607
Semiconductor memory device and method of performing setting operation in semiconductor memory device Sep 15, 2014 Issued
Array ( [id] => 11681917 [patent_doc_number] => 09680460 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-06-13 [patent_title] => 'Signal transmission method of semiconductor integrated circuit for transmitting signal to a plurality of stacked semiconductor chips' [patent_app_type] => utility [patent_app_number] => 14/487816 [patent_app_country] => US [patent_app_date] => 2014-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 5449 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14487816 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/487816
Signal transmission method of semiconductor integrated circuit for transmitting signal to a plurality of stacked semiconductor chips Sep 15, 2014 Issued
Array ( [id] => 10732786 [patent_doc_number] => 20160078937 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-03-17 [patent_title] => 'RESISTIVE MEMORY DEVICE AND CONTROL METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 14/487399 [patent_app_country] => US [patent_app_date] => 2014-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4022 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14487399 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/487399
RESISTIVE MEMORY DEVICE AND CONTROL METHOD THEREOF Sep 15, 2014 Abandoned
Array ( [id] => 10417903 [patent_doc_number] => 20150302913 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-10-22 [patent_title] => 'VOLATILE MEMORY DEVICE, MEMORY MODULE INCLUDING THE SAME, AND METHOD OF OPERATING MEMORY MODULE' [patent_app_type] => utility [patent_app_number] => 14/486529 [patent_app_country] => US [patent_app_date] => 2014-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5877 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14486529 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/486529
VOLATILE MEMORY DEVICE, MEMORY MODULE INCLUDING THE SAME, AND METHOD OF OPERATING MEMORY MODULE Sep 14, 2014 Abandoned
Array ( [id] => 10666739 [patent_doc_number] => 20160012884 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-01-14 [patent_title] => 'MEMORY SYSTEM AND METHOD OF OPERATION OF THE SAME' [patent_app_type] => utility [patent_app_number] => 14/480951 [patent_app_country] => US [patent_app_date] => 2014-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 12329 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14480951 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/480951
MEMORY SYSTEM AND METHOD OF OPERATION OF THE SAME Sep 8, 2014 Abandoned
Array ( [id] => 10610752 [patent_doc_number] => 09330788 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-05-03 [patent_title] => 'Semiconductor integrated circuit capable of performing self-test' [patent_app_type] => utility [patent_app_number] => 14/481161 [patent_app_country] => US [patent_app_date] => 2014-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 11724 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 280 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14481161 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/481161
Semiconductor integrated circuit capable of performing self-test Sep 8, 2014 Issued
Array ( [id] => 13145371 [patent_doc_number] => 10090023 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-10-02 [patent_title] => Memory device including memory circuit and selection circuit [patent_app_type] => utility [patent_app_number] => 14/479707 [patent_app_country] => US [patent_app_date] => 2014-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 35 [patent_figures_cnt] => 49 [patent_no_of_words] => 21952 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 206 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14479707 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/479707
Memory device including memory circuit and selection circuit Sep 7, 2014 Issued
Array ( [id] => 10224882 [patent_doc_number] => 20150109875 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-04-23 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 14/479025 [patent_app_country] => US [patent_app_date] => 2014-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 11044 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14479025 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/479025
Ferroelectric memory device and timing circuit to control the boost level of a word line Sep 4, 2014 Issued
Array ( [id] => 11240401 [patent_doc_number] => 09467050 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-10-11 [patent_title] => 'Semiconductor apparatus having transfer circuit transferring high voltage' [patent_app_type] => utility [patent_app_number] => 14/477593 [patent_app_country] => US [patent_app_date] => 2014-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 5063 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14477593 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/477593
Semiconductor apparatus having transfer circuit transferring high voltage Sep 3, 2014 Issued
Array ( [id] => 10631269 [patent_doc_number] => 09349423 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-05-24 [patent_title] => 'Single node power management for multiple memory devices' [patent_app_type] => utility [patent_app_number] => 14/476323 [patent_app_country] => US [patent_app_date] => 2014-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 9347 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14476323 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/476323
Single node power management for multiple memory devices Sep 2, 2014 Issued
Array ( [id] => 10703059 [patent_doc_number] => 20160049206 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-02-18 [patent_title] => 'High Voltage Step Down Regulator with Breakdown Protection' [patent_app_type] => utility [patent_app_number] => 14/459795 [patent_app_country] => US [patent_app_date] => 2014-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 7306 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14459795 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/459795
High voltage step down regulator with breakdown protection Aug 13, 2014 Issued
Array ( [id] => 10385006 [patent_doc_number] => 20150270014 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-09-24 [patent_title] => 'Fault Detection and Prediction for Data Storage Elements' [patent_app_type] => utility [patent_app_number] => 14/454683 [patent_app_country] => US [patent_app_date] => 2014-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 13193 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14454683 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/454683
Fault detection and prediction for data storage elements Aug 6, 2014 Issued
Array ( [id] => 14854981 [patent_doc_number] => 10416210 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-09-17 [patent_title] => Method for measuring dynamics of a flow of energy and relevant device and system [patent_app_type] => utility [patent_app_number] => 14/910411 [patent_app_country] => US [patent_app_date] => 2014-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7737 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14910411 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/910411
Method for measuring dynamics of a flow of energy and relevant device and system Aug 5, 2014 Issued
Array ( [id] => 10681332 [patent_doc_number] => 20160027477 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-01-28 [patent_title] => 'INTERLEAVED GROUPED WORD LINES FOR THREE DIMESIONAL NON-VOLATILE STORAGE' [patent_app_type] => utility [patent_app_number] => 14/341519 [patent_app_country] => US [patent_app_date] => 2014-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 27 [patent_no_of_words] => 25818 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14341519 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/341519
Interleaved grouped word lines for three dimensional non-volatile storage Jul 24, 2014 Issued
Array ( [id] => 11517252 [patent_doc_number] => 20170084326 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-23 [patent_title] => 'A NEGATIVE DIFFERENTIAL RESISTANCE BASED MEMORY' [patent_app_type] => utility [patent_app_number] => 15/126255 [patent_app_country] => US [patent_app_date] => 2014-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8812 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15126255 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/126255
A NEGATIVE DIFFERENTIAL RESISTANCE BASED MEMORY Jul 7, 2014 Abandoned
Array ( [id] => 10394440 [patent_doc_number] => 20150279446 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-10-01 [patent_title] => 'METHOD, APPARATUS AND SYSTEM FOR DETERMINING A WRITE RECOVERY TIME OF A MEMORY BASED ON TEMPERATURE' [patent_app_type] => utility [patent_app_number] => 14/227969 [patent_app_country] => US [patent_app_date] => 2014-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8026 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14227969 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/227969
Method, apparatus and system for determining a write recovery time of a memory based on temperature Mar 26, 2014 Issued
Array ( [id] => 10666736 [patent_doc_number] => 20160012882 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-01-14 [patent_title] => 'Flux Latching Superconducting Memory' [patent_app_type] => utility [patent_app_number] => 14/769655 [patent_app_country] => US [patent_app_date] => 2014-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2625 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14769655 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/769655
Flux Latching Superconducting Memory Mar 13, 2014 Abandoned
Array ( [id] => 11273515 [patent_doc_number] => 20160336062 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-11-17 [patent_title] => 'ACCESSING A RESISTIVE STORAGE ELEMENT-BASED MEMORY CELL ARRAY' [patent_app_type] => utility [patent_app_number] => 15/111185 [patent_app_country] => US [patent_app_date] => 2014-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3007 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15111185 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/111185
ACCESSING A RESISTIVE STORAGE ELEMENT-BASED MEMORY CELL ARRAY Jan 30, 2014 Abandoned
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