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Alfredo Bermudez Lozada

Examiner (ID: 7463, Phone: (571)272-0877 , Office: P/2825 )

Most Active Art Unit
2825
Art Unit(s)
2825
Total Applications
617
Issued Applications
490
Pending Applications
86
Abandoned Applications
57

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 20338774 [patent_doc_number] => 20250342894 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-11-06 [patent_title] => METHODS, DEVICES, AND SYSTEMS FOR ANOMALY DETECTION FOR NON-VOLATILE MEMORY DEVICE PROGRAMMING [patent_app_type] => utility [patent_app_number] => 18/653446 [patent_app_country] => US [patent_app_date] => 2024-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 29247 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18653446 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/653446
METHODS, DEVICES, AND SYSTEMS FOR ANOMALY DETECTION FOR NON-VOLATILE MEMORY DEVICE PROGRAMMING May 1, 2024 Pending
Array ( [id] => 19531500 [patent_doc_number] => 20240355402 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-24 [patent_title] => KNOWN-FAILURE ERROR HANDLING IN A MEMORY SUB-SYSTEM [patent_app_type] => utility [patent_app_number] => 18/637913 [patent_app_country] => US [patent_app_date] => 2024-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13497 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18637913 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/637913
KNOWN-FAILURE ERROR HANDLING IN A MEMORY SUB-SYSTEM Apr 16, 2024 Issued
Array ( [id] => 20648181 [patent_doc_number] => 12603131 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-04-14 [patent_title] => Gate-controlled thyristor and CAM array [patent_app_type] => utility [patent_app_number] => 18/636277 [patent_app_country] => US [patent_app_date] => 2024-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 17 [patent_no_of_words] => 2697 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 212 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18636277 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/636277
Gate-controlled thyristor and CAM array Apr 15, 2024 Issued
Array ( [id] => 19603097 [patent_doc_number] => 20240393977 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-28 [patent_title] => PRE-PROGRAM PASS TO REDUCE SYSTEM BUFFER REQUIREMENT WHEN PROGRAMMING QUAD-LEVEL CELL (QLC) MEMORY [patent_app_type] => utility [patent_app_number] => 18/636584 [patent_app_country] => US [patent_app_date] => 2024-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12432 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18636584 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/636584
PRE-PROGRAM PASS TO REDUCE SYSTEM BUFFER REQUIREMENT WHEN PROGRAMMING QUAD-LEVEL CELL (QLC) MEMORY Apr 15, 2024 Pending
Array ( [id] => 20065636 [patent_doc_number] => 20250203858 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-06-19 [patent_title] => MULTI-WRITE READ-ONLY MEMORY ARRAY AND READ-ONLY MEMORY THEREOF [patent_app_type] => utility [patent_app_number] => 18/624418 [patent_app_country] => US [patent_app_date] => 2024-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8281 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -59 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18624418 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/624418
MULTI-WRITE READ-ONLY MEMORY ARRAY AND READ-ONLY MEMORY THEREOF Apr 1, 2024 Pending
Array ( [id] => 19321221 [patent_doc_number] => 20240242767 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-18 [patent_title] => STORAGE DEVICE FOR GENERATING IDENTITY CODE AND IDENTITY CODE GENERATING METHOD [patent_app_type] => utility [patent_app_number] => 18/623116 [patent_app_country] => US [patent_app_date] => 2024-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5180 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18623116 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/623116
Storage device for generating identity code and identity code generating method Mar 31, 2024 Issued
Array ( [id] => 19483745 [patent_doc_number] => 20240331787 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-03 [patent_title] => START-UP CIRCUIT FOR BANDGAP REFERENCES IN A NAND FLASH [patent_app_type] => utility [patent_app_number] => 18/618456 [patent_app_country] => US [patent_app_date] => 2024-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4515 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18618456 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/618456
START-UP CIRCUIT FOR BANDGAP REFERENCES IN A NAND FLASH Mar 26, 2024 Pending
Array ( [id] => 19515397 [patent_doc_number] => 20240347083 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-17 [patent_title] => TECHNIQUES TO MITIGATE MEMORY DIE MISALIGNMENT [patent_app_type] => utility [patent_app_number] => 18/614244 [patent_app_country] => US [patent_app_date] => 2024-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15247 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18614244 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/614244
Techniques to mitigate memory die misalignment Mar 21, 2024 Issued
Array ( [id] => 19765696 [patent_doc_number] => 12223994 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-02-11 [patent_title] => Memory arrays, ferroelectric transistors, and methods of reading and writing relative to memory cells of memory arrays [patent_app_type] => utility [patent_app_number] => 18/606333 [patent_app_country] => US [patent_app_date] => 2024-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5873 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 219 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18606333 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/606333
Memory arrays, ferroelectric transistors, and methods of reading and writing relative to memory cells of memory arrays Mar 14, 2024 Issued
Array ( [id] => 19574872 [patent_doc_number] => 20240379164 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-14 [patent_title] => METHOD OF PROGRAMMING DATA IN NONVOLATILE MEMORY DEVICE AND NONVOLATILE MEMORY DEVICE PERFORMING THE SAME [patent_app_type] => utility [patent_app_number] => 18/602636 [patent_app_country] => US [patent_app_date] => 2024-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 21184 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18602636 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/602636
METHOD OF PROGRAMMING DATA IN NONVOLATILE MEMORY DEVICE AND NONVOLATILE MEMORY DEVICE PERFORMING THE SAME Mar 11, 2024 Pending
Array ( [id] => 20222757 [patent_doc_number] => 20250285688 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-09-11 [patent_title] => NON-VOLATILE MEMORY WITH PROGRAM-VERIFY AT COMMON VOLTAGE [patent_app_type] => utility [patent_app_number] => 18/601389 [patent_app_country] => US [patent_app_date] => 2024-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13120 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18601389 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/601389
NON-VOLATILE MEMORY WITH PROGRAM-VERIFY AT COMMON VOLTAGE Mar 10, 2024 Pending
Array ( [id] => 20868024 [patent_doc_number] => 12694932 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-07-28 [patent_title] => Memory device configured to apply different voltages to wirings depending on a current flowing through corresponding memory strings [patent_app_type] => utility [patent_app_number] => 18/596541 [patent_app_country] => US [patent_app_date] => 2024-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 16 [patent_no_of_words] => 3835 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 269 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18596541 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/596541
MEMORY DEVICE AND METHOD Mar 4, 2024 Issued
Array ( [id] => 20530162 [patent_doc_number] => 12548603 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-02-10 [patent_title] => Semiconductor storage device comprising a replica bit line circuit [patent_app_type] => utility [patent_app_number] => 18/594877 [patent_app_country] => US [patent_app_date] => 2024-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 1144 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 349 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18594877 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/594877
Semiconductor storage device comprising a replica bit line circuit Mar 3, 2024 Issued
Array ( [id] => 19434689 [patent_doc_number] => 20240303187 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-12 [patent_title] => PARTIALLY PROGRAMMED BLOCK READ OPERATIONS [patent_app_type] => utility [patent_app_number] => 18/591368 [patent_app_country] => US [patent_app_date] => 2024-02-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6024 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18591368 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/591368
PARTIALLY PROGRAMMED BLOCK READ OPERATIONS Feb 28, 2024 Pending
Array ( [id] => 20611030 [patent_doc_number] => 12586635 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-03-24 [patent_title] => Static random access memory with write assist circuit [patent_app_type] => utility [patent_app_number] => 18/590490 [patent_app_country] => US [patent_app_date] => 2024-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4443 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18590490 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/590490
Static random access memory with write assist circuit Feb 27, 2024 Issued
Array ( [id] => 19237063 [patent_doc_number] => 20240194258 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-13 [patent_title] => MEMORY DEVICE AND METHOD FOR OPERATING THE SAME [patent_app_type] => utility [patent_app_number] => 18/586174 [patent_app_country] => US [patent_app_date] => 2024-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10392 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18586174 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/586174
Memory device and method for operating the same including setting a recovery voltage Feb 22, 2024 Issued
Array ( [id] => 20674067 [patent_doc_number] => 12614587 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-04-28 [patent_title] => Resistance change element, storage device, and neural network apparatus [patent_app_type] => utility [patent_app_number] => 18/584183 [patent_app_country] => US [patent_app_date] => 2024-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 16 [patent_no_of_words] => 9364 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 232 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18584183 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/584183
Resistance change element, storage device, and neural network apparatus Feb 21, 2024 Issued
Array ( [id] => 20196553 [patent_doc_number] => 20250273263 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-08-28 [patent_title] => DYNAMIC ADJUSTMENT OF SIGNAL DELAY WITH MEMORY ARRAY VOLTAGE [patent_app_type] => utility [patent_app_number] => 18/584023 [patent_app_country] => US [patent_app_date] => 2024-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10922 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18584023 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/584023
Dynamic adjustment of signal delay with memory array voltage Feb 21, 2024 Issued
Array ( [id] => 19348899 [patent_doc_number] => 20240257863 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-01 [patent_title] => MEMORIES AND MEMORY COMPONENTS WITH INTERCONNECTED AND REDUNDANT DATA INTERFACES [patent_app_type] => utility [patent_app_number] => 18/584371 [patent_app_country] => US [patent_app_date] => 2024-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10036 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18584371 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/584371
MEMORIES AND MEMORY COMPONENTS WITH INTERCONNECTED AND REDUNDANT DATA INTERFACES Feb 21, 2024 Pending
Array ( [id] => 19866012 [patent_doc_number] => 20250104798 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-27 [patent_title] => CONTROLLER FOR MANAGING BAD BLOCK, STORAGE DEVICE INCLUDING THE SAME, AND METHOD OF OPERATING THE STORAGE DEVICE [patent_app_type] => utility [patent_app_number] => 18/582654 [patent_app_country] => US [patent_app_date] => 2024-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5419 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18582654 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/582654
Controller for managing bad block, storage device including the same, and method of operating the storage device Feb 20, 2024 Issued
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